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5962-9463701MXC PDF预览

5962-9463701MXC

更新时间: 2024-02-07 14:10:43
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
12页 245K
描述
IC 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, QFP68, QCC-68, Analog to Digital Converter

5962-9463701MXC 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QFP,针数:68
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N最大模拟输入电压:1.75 V
最小模拟输入电压:-1.75 V转换器类型:ADC, FLASH METHOD
JESD-30 代码:S-XQFP-G68JESD-609代码:e4
长度:24.13 mm最大线性误差 (EL):0.293%
标称负供电电压:-5 V模拟输入通道数量:1
位数:10功能数量:1
端子数量:68最高工作温度:125 °C
最低工作温度:-55 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:UNSPECIFIED
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
采样速率:60 MHz筛选级别:MIL-STD-883
标称供电电压:5 V表面贴装:YES
温度等级:MILITARY端子面层:GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:QUAD宽度:24.13 mm
Base Number Matches:1

5962-9463701MXC 数据手册

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AD9020  
noise. The noise is the sum of all other spectral components,  
including harmonic distortion, but excluding dc.  
THEORY OF OPERATION  
Refer to the AD9020 block diagram. As shown, the AD9020  
uses a modified “flash,” or parallel, A/D architecture. The  
analog input range is determined by an external voltage refer-  
ence (+VREF and –VREF), nominally 1.75 V. An internal  
resistor ladder divides this reference into 512 steps, each rep-  
resenting two quantization levels. Taps along the resistor ladder  
(1/4REF, 1/2REF and 3/4REF) are provided to optimize linearity.  
Rated performance is achieved by driving these points at 1/4,  
1/2, and 3/4, respectively, of the voltage reference range.  
Good receiver design minimizes the level of spurious signals  
in the system. Spurious signals developed in the ADC are the  
result of imperfections (nonlinearities, delay mismatch, vary-  
ing input impedance, etc.) in the device transfer function.  
In the ADC, these spurious signals appear as Harmonic Dis-  
tortion. Harmonic Distortion is also measured with an FFT  
and is specified as the ratio of the fundamental component of  
the signal (rms amplitude) to the rms value of the worst-case  
harmonic (usually the 2nd or 3rd).  
The A/D conversion for the nine most significant bits (MSBs)  
is performed by 512 comparators. The value of the least sig-  
nificant bit (LSB) is determined by a unique interpolation  
scheme between adjacent comparators. The decoding logic  
processes the comparator outputs and provides a 10-bit code  
to the output stage of the converter.  
Two-Tone Intermodulation Distortion (IMD) is a frequently  
cited specification in receiver design. In narrow-band receiv-  
ers, third-order IMD products result in spurious signals in  
the passband of the receiver. Like mixers and amplifiers, the  
ADC is characterized with two, equal-amplitude, pure input  
frequencies. The IMD equals the ratio of the power of either  
of the two input signals to the power of the strongest third-  
order IMD signal. Unlike mixers and amplifiers, the IMD  
does not always behave as it does in linear devices (reduced  
input levels do not result in predictable reductions in IMD).  
Flash architecture has an advantage over other A/D architec-  
tures because conversion occurs in one step. This means the  
performance of the converter is primarily limited by the speed  
and matching of the individual comparators. In the AD9020,  
an innovative interpolation scheme takes advantage of flash  
architecture but minimizes the input capacitance, power and  
device count usually associated with that method of conversion.  
Performance graphs provide typical harmonic and SNR data  
for the AD9020 for increasing analog input frequencies. In  
choosing an A/D converter, always look at the dynamic range  
for the analog input frequency of interest. The AD9020  
specifications provide guaranteed minimum limits at three  
analog test frequencies.  
These advantages occur by using only half the normal num-  
ber of input comparator cells to accomplish the conversion.  
In addition, a proprietary decoding scheme minimizes error  
codes. Input control pins allow the user to select from among  
Binary, Inverted Binary, Two’s Complement and Inverted  
Two’s Complement coding (see Table I).  
Aperture Delay is the delay between the rising edge of the  
ENCODE command and the instant at which the analog input is  
sampled. Many systems require simultaneous sampling of  
more than one analog input signal with multiple ADCs. In  
these situations, timing is critical and the absolute value of the  
aperture delay is not as critical as the matching between devices.  
APPLICATIONS  
Many of the specifications used to describe analog/digital  
converters have evolved from system performance require-  
ments in these applications. Different systems emphasize  
particular specifications, depending on how the part is used.  
The following applications highlight some of the specifications  
and features that make the AD9020 attractive in these systems.  
Aperture Uncertainty, or jitter, is the sample-to-sample variation in  
aperture delay. This is especially important when sampling high  
slew rate signals in wide bandwidth systems. Aperture uncertainty  
is one of the factors that degrade dynamic performance as the ana-  
log input frequency is increased.  
Wideband Receivers  
Radar and communication receivers (baseband and direct IF  
digitization), ultrasound medical imaging, signal intelligence  
and spectral analysis all place stringent ac performance require-  
ments on analog-to-digital converters (ADCs).  
Digitizing Oscilloscopes  
Oscilloscopes provide amplitude information about an observed  
waveform with respect to time. Digitizing oscilloscopes must  
accurately sample this signal, without distorting the information  
to be displayed.  
Frequency domain characterization of the AD9020 provides sig-  
nal-to-noise ratio (SNR) and harmonic distortion data to  
simplify selection of the ADC.  
One figure of merit for the ADC in these applications is Effective  
Number of Bits (ENOBs). ENOB is calculated with a sine wave  
curve fit and equals:  
Receiver sensitivity is limited by the Signal-to-Noise Ratio of  
the system. The SNR for an ADC is measured in the fre-  
quency domain and calculated with a Fast Fourier Transform  
(FFT). The SNR equals the ratio of the fundamental compo-  
nent of the signal (rms amplitude) to the rms value of the  
ENOB = N – LOG2 [Error (measured)/Error (ideal)]  
N is the resolution (number of bits) of the ADC. The measured  
error is the actual rms error calculated from the converter out-  
puts with a pure sine wave input.  
The Analog Bandwidth of the converter is the analog input fre-  
quency at which the spectral power of the fundamental signal is  
reduced 3 dB from its low frequency value. The analog band-  
width is a good indicator of a converter’s stewing capabilities.  
REV. C  
–6–  

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