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5962-9451801MLA PDF预览

5962-9451801MLA

更新时间： 2024-01-08 12:14:58
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理转换器
页数 文件大小 规格书
12页 184K
描述
LC2MOS Complete, Dual 12-Bit MDAC, (8 + 4) Loading Structure

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中文翻译

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5962-9451801MLA 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.06
Is Samacsys：N最大模拟输出电压：10 V
最小模拟输出电压：-10 V转换器类型：D/A CONVERTER
输入位码：BINARY, OFFSET BINARY输入格式：PARALLEL, WORD
JESD-30 代码：R-GDIP-T24JESD-609代码：e0
最大线性误差 (EL)：0.0244%标称负供电电压：-15 V
位数：12功能数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE电源：+-15 V
认证状态：Qualified筛选级别：MIL-STD-883
座面最大高度：5.715 mm标称安定时间 (tstl)：3 µs
子类别：Other Converters最大压摆率：10 mA
标称供电电压：15 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE宽度：7.62 mm
Base Number Matches：1

5962-9451801MLA 数据手册

 浏览型号5962-9451801MLA的Datasheet PDF文件第6页浏览型号5962-9451801MLA的Datasheet PDF文件第7页浏览型号5962-9451801MLA的Datasheet PDF文件第8页浏览型号5962-9451801MLA的Datasheet PDF文件第10页浏览型号5962-9451801MLA的Datasheet PDF文件第11页浏览型号5962-9451801MLA的Datasheet PDF文件第12页 
AD7837/AD7847  
BIPOLAR OPERATION  
(4-QUADRANT MULTIPLICATION)  
APPLICATIONS  
PROGRAMMABLE GAIN AMPLIFIER (PGA)  
Figure 16 shows the AD7837/AD7847 connected for bipolar  
operation. The coding is offset binary as shown in Table IV.  
When VIN is an ac signal, the circuit performs 4-quadrant multi-  
plication. To maintain the gain error specifications, resistors R1,  
R2 and R3 should be ratio matched to 0.01%. Note that on the  
AD7847 the feedback resistor RFB is internally connected to  
The dual DAC/amplifier combination along with access to RFB  
make the AD7837 ideal as a programmable gain amplifier. In this  
application, the DAC functions as a programmable resistor in the  
amplifier feedback loop. This type of configuration is shown  
in Figure 17 and is suitable for ac gain control. The circuit con-  
sists of two PGAs in series. Use of a dual configuration provides  
greater accuracy over a wider dynamic range than a single PGA  
solution. The overall system gain is the product of the individual  
gain stages. The effective gains for each stage are controlled by  
the DAC codes. As the code decreases, the effective DAC  
resistance increases, and so the gain also increases.  
VOUT  
.
R2  
20kꢁ  
R1  
20kꢁ  
V
AD711  
DD  
V
OUT  
V
AD7837  
AD7847  
DD  
R
V
FBA  
V
*
REFA  
R3  
10kꢁ  
DAC A  
V
R
OUTA  
REFA  
FBA  
DAC A  
V
V
V
IN  
IN  
OUTA  
*INTERNALLY  
CONNECTED  
ON AD7847  
AGNDA  
V
DGND AGNDA  
SS  
AD7837  
R
V
REFB  
DAC B  
V
SS  
FBB  
V
OUTB  
Figure 16. Bipolar Offset Binary Operation  
V
OUT  
AGNDB  
Table IV. Bipolar Code Table  
Figure 17. Dual PGA Circuit  
The transfer function is given by  
DAC Latch Contents  
MSB LSB  
Analog Output, VOUT  
REQA REQB  
×
VOUT  
VIN  
2047  
=
(1)  
+VIN  
×
×
1111 1111 1111  
RFBA RFBB  
2048  
where REQA, REQB are the effective DAC resistances controlled  
by the digital input code:  
1
2048  
+VIN  
0 V  
1000 0000 0001  
1000 0000 0000  
212 RIN  
REQ  
=
(2)  
N
1
2048  
where RIN is the DAC input resistance and is equal to RFB and  
N = DAC input code in decimal.  
–VIN  
×
×
0111 1111 1111  
0000 0000 0000  
The transfer function in (1) thus simplifies to  
2048  
–VIN  
= –VIN  
2048  
VOUT  
VIN  
212 212  
×
=
(3)  
NA NB  
VIN  
Note 1 LSB =  
2048  
.
where NA = DAC A input code in decimal and NB = DAC B  
input code in decimal.  
NA, NB may be programmed between 1 and (212–1). The zero  
code is not allowed as it results in an open loop amplifier  
response. To minimize errors, the digital codes NA and NB  
should be chosen to be equal to or as close as possible to each  
other to achieve the required gain.  
REV. C  
–9–  
1...6789101112

中文翻译

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5962-9451801MLA 替代型号

型号 品牌 替代类型 描述 数据表
MX7837AN+ MAXIM

类似代替

 		D/A Converter, 2 Func, Parallel, 8 Bits Input Loading, 4us Settling Time, PDIP24, PLASTIC,
AD7837ANZ ADI

功能相似

 		LC MOS COMPLETE, DUAL 12-BIT MDACS

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