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5962-9323901QXA PDF预览

5962-9323901QXA

更新时间： 2024-02-28 06:22:25
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路
页数 文件大小 规格书
28页 484K
描述
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS

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5962-9323901QXA 技术参数

生命周期：Active零件包装代码：DIP
包装说明：0.300 INCH, CERAMIC, DIP-28针数：28
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.06Is Samacsys：N
外部数据总线宽度：JESD-30 代码：R-GDIP-T28
长度：36.83 mm端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Qualified
筛选级别：MIL-PRF-38535 Class Q座面最大高度：5.08 mm
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

5962-9323901QXA 数据手册

 浏览型号5962-9323901QXA的Datasheet PDF文件第4页浏览型号5962-9323901QXA的Datasheet PDF文件第5页浏览型号5962-9323901QXA的Datasheet PDF文件第6页浏览型号5962-9323901QXA的Datasheet PDF文件第8页浏览型号5962-9323901QXA的Datasheet PDF文件第9页浏览型号5962-9323901QXA的Datasheet PDF文件第10页 
SN54ACT8997, SN74ACT8997  
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES  
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS  
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996  
Exit1-IR, Exit2-IR  
These are temporary states that end the shifting process. It is possible to return to the Shift-IR state from either  
Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which  
the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state  
on the falling edge of TCK in Exit1-IR.  
Pause-IR  
TheTAPcanremaininthisstateindefinitely. ThePause-IRstatesuspendsandresumesshiftoperationswithout  
loss of data.  
Update-IR  
In this state, the latches shadowing the instruction register are updated with the new instruction.  
instruction-register description  
The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the  
instructions implemented in the ’ACT8997 and the data register selected by each instruction. The MSB of the  
IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error  
signal (IRERR) is generated internally as shown in Table 3. The ’ACT8997 can be configured to output IRERR  
via DCO if the TAP enters the Pause-IR state.  
During the Capture-IR state, the IR status word is loaded.The IR status word contains information about the  
most recently loaded value of the instruction register and the logic level present at the DCI input. The IR status  
word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR.  
Bit 7  
(MSB)  
Bit 0  
(LSB)  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
TDI or DTDI  
TDO  
Figure 2. Instruction-Register Bits and Order of Scan  
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1...45678910...28

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