M672061F
puts Q0-Q8 by pulsing R low. The offset options are listed in table 1. If PHF is not loaded
during the reset cycle, the default offset will be the half of the total memory of the device.
The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the
difference between the write and read pointers is less than or equal to the Programma-
ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half
of the total memory (if the Half Full register has not been loaded during the reset cycle).
After half the memory is filled and on the falling edge of the next write operation, the
Half-Full Flag (HF) will be set to low and will remain set until the difference between the
write and read pointers is less than or equal to half of the total memory of the device.
The Half-Full Flag (HF) is then reset by the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of
the previous device. This output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device reaches the last memory
location.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever
Read (R) is in a high state.
6
Rev. E–20-Aug-01