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5962-9317706VZX PDF预览

5962-9317706VZX

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
TEMIC 先进先出芯片
页数 文件大小 规格书
22页 382K
描述
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28

5962-9317706VZX 数据手册

 浏览型号5962-9317706VZX的Datasheet PDF文件第1页浏览型号5962-9317706VZX的Datasheet PDF文件第2页浏览型号5962-9317706VZX的Datasheet PDF文件第3页浏览型号5962-9317706VZX的Datasheet PDF文件第5页浏览型号5962-9317706VZX的Datasheet PDF文件第6页浏览型号5962-9317706VZX的Datasheet PDF文件第7页 
M672061F  
Signal Description  
Data In (I0 - I8)  
Data inputs for 9 - bit data  
Reset (RS)  
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both  
internal read and write pointers to the first location. A reset is required after power-up  
before a write operation can be enabled. Both the Read Enable (R) and Write Enable  
(W) inputs must be in the high state during the period shown in Figure 2 (i.e. tRSS before  
the rising edge of RS) and should not change until tRSR after the rising edge of RS.  
Otherwise, pulse write (or read) low during the reset operation loads the Programmable  
Half Full Flag register from the data Inputs I0-I8 (or data outputs Q0-Q8) (shown in fig-  
ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are  
reseted to high and the Empty Flag to low.  
Figure 1. Reset (no write to Programmable Half Full Flag register)  
Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC  
2. W and R = VIH around the rising edge of RS.  
.
Figure 2. Reset (write (read) to Programmable Half Full Flag register)  
Write Enable (W)  
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.  
Data set-up and hold times must be maintained in the rise time of the leading edge of  
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any  
current read operation.  
4
Rev. E20-Aug-01  

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