PALCE16V8
Selection Guide
tPD ns
Com’l/Ind
tS ns
Com’l/Ind
tCO ns
Com’l/Ind
ICC mA
Generic Part Number
PALCE16V8-5
Mil
Mil
Mil
Com’l
115
115
90
Mil/Ind
5
3
4
PALCE16V8-7
7.5
10
15
25
15
25
7
5
PALCE16V8-10
PALCE16V8-15
PALCE16V8-25
PALCE16V8L-15
PALCE16V8L-25
10
15
25
15
25
10
12
15
12
15
10
12
20
12
20
7
10
10
12
12
20
130
130
130
65
10
12
10
12
90
90
55
55
65
Shaded area contains preliminary information.
Power-Up Reset
Functional Description (continued)
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip car-
rier, and a 20-lead square plastic leaded chip carrier.
Electronic Signature
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Configuration Table
CG0
CG1
CL0x
Cell Configuration
Devices Emulated
Registered Med PALs
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Registered Med PALs
Small PALs
Small PALs
Combinatorial I/O
16L8 only
Document #: 38-03025 Rev. **
Page 2 of 13
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