PALCE16V8
Commercial and Industrial Switching Characteristics[2]
16V8-5
16V8-7
16V8-10
16V8-15
16V8-25
Parameter
Description
Input to Output
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tPD
1
5
3
7.5
3
10
3
15
3
25
ns
Propagation
Delay[8, 9]
tPZX
tPXZ
tEA
tER
tCO
tS
OE to Output
Enable
1
1
1
1
1
3
6
5
6
5
4
6
6
9
9
5
10
10
10
10
7
15
15
15
15
10
20
20
25
25
12
ns
ns
ns
ns
ns
ns
OE to Output
Disable
Input to Output
Enable Delay[7]
Input to Output
Disable Delay[7, 10]
Clock to Output
Delay[8,9]
2
5
2
2
2
Input or Feedback
Set-Up Time
7.5
12
15
tH
tP
Input Hold Time
0
7
0
0
0
0
ns
ns
External Clock
Period (tCO + tS)
10
14.5
22
27
tWH
Clock Width HIGH[7]
Clock Width LOW[7]
3
3
4
4
6
6
8
8
12
12
37
ns
ns
tWL
fMAX1
External Maximum
Frequency
143
100
69
45.5
MHz
(1/(tCO + tS))[7, 11]
fMAX2
fMAX3
Data Path Maximum Fre-
quency (1/(tWH + tWL))[7, 12]
166
166
125
125
83
74
62.5
50
41.6
40
MHz
MHz
Internal Feedback
Maximum Frequency
(1/(tCF + tS))[7, 13]
tCF
tPR
Register Clock to
3
3
6
8
10
ns
Feedback Input[7, 14]
Power-Up Reset Time[7]
1
1
1
1
1
µs
Shaded area contains preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in a given access cycle.
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.
Document #: 38-03025 Rev. **
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