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5962-8876404XX

更新时间： 2024-01-13 19:08:30
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
16页 286K
描述
High Speed , 8-Channel, 8-Bit CMOS ADC

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5962-8876404XX 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：28
Reach Compliance Code：unknown风险等级：5.7
Is Samacsys：N最大模拟输入电压：5 V
最小模拟输入电压：最长转换时间：2 µs
转换器类型：ADC, FLASH METHODJESD-30 代码：R-GDIP-T28
JESD-609代码：e0湿度敏感等级：NOT APPLICABLE
模拟输入通道数量：8位数：8
功能数量：1端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：BINARY, COMPLEMENTARY OFFSET BINARY输出格式：PARALLEL, 8 BITS
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE采样速率：0.05 MHz
采样并保持/跟踪并保持：TRACK座面最大高度：5.59 mm
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE宽度：15.24 mm
Base Number Matches：1

5962-8876404XX 数据手册

 浏览型号5962-8876404XX的Datasheet PDF文件第7页浏览型号5962-8876404XX的Datasheet PDF文件第8页浏览型号5962-8876404XX的Datasheet PDF文件第9页浏览型号5962-8876404XX的Datasheet PDF文件第11页浏览型号5962-8876404XX的Datasheet PDF文件第12页浏览型号5962-8876404XX的Datasheet PDF文件第13页 
AD7824/AD7828  
to any of the addresses in Table II starts a conversion and reads  
the conversion result.  
MICROPROCESSOR INTERFACING  
The AD7824/AD7828 is designed to interface to microprocessors  
as Read Only Memory (ROM). Analog channel selection, con-  
version start, and data read operations are controlled by CS, RD,  
and the channel address inputs. These signals are common to  
all memory peripheral devices.  
MOVE × B $C000, D0  
Once conversion has begun, the MC68000 inserts WAIT states  
until INT goes low, asserting DTACK at the end of conversion.  
The microprocessor then places the conversion results into the  
D0 register.  
Z80 MICROPROCESSOR  
Figure 16 shows a typical AD7824/AD7828–Z80 interface. The  
AD7824/AD7828 is operating in Mode 0. Assume the ADC is  
assigned a memory block starting at address C000. The follow-  
ing LOAD instruction to any of the addresses listed in Table II  
will start a conversion of the selected channel and read the  
conversion result.  
A23  
A2  
A1  
ADDRESS BUS  
A0  
A1  
A0 A1 A2**  
CS  
ADDRESS  
DECODE  
AS  
EN  
LD B, (C000)  
R/W  
RD  
At the beginning of the instruction cycle when the ADC  
address is selected, RDY asserts the WAIT input so that the  
Z80 is forced into a WAIT state. At the end of conversion,  
RDY returns high and the conversion result is placed in the B  
register of the microprocessor.  
CLR  
7474  
MC68000  
AD7824*  
AD7828*  
5V  
5k⍀  
D
DTACK  
CK  
RDY  
DB7  
Q
D7  
DATA BUS  
A15  
A2  
A1  
D0  
ADDRESS BUS  
DB0  
A0  
A0  
A0 A1 A2**  
ADDRESS  
DECODE  
EN  
MREQ  
Z80  
*
**  
LINEAR CIRCUITRY OMITTED FOR CLARITY.  
FORTHE AD7828 ONLY  
5V  
5k⍀  
CS  
AD7824*  
AD7828*  
Figure 17. AD7824/AD7828–MC68000 Interface  
RDY  
WAIT  
RD  
RD  
TMS32010 MICROCOMPUTER  
D7  
DB7  
A TMS32010 interface is shown in Figure 18. The AD7824/  
AD7828 is operating in Mode 1 (i.e., no µP WAIT states). The  
ADC is mapped at a port address. The following I/O instruction  
starts a conversion and reads the previous conversion result into  
the accumulator.  
DATA BUS  
D0  
DB0  
IN, A PA (PA = PORT ADDRESS)  
*
**  
LINEAR CIRCUITRY OMITTED FOR CLARITY.  
FORTHE AD7828 ONLY  
The port address (000 to 111) selects the analog channel to be  
converted. When conversion is complete, a second I/O instruc-  
tion (IN, A PA) reads the up-to-date data into the accumulator  
and starts another conversion. A delay of 2.5 µs must be allowed  
between conversions.  
Figure 16. AD7824/AD7828–Z80 lnterface  
Table II. Address Channel Selection  
AD7824  
Channel  
AD7828  
Channel  
Address  
PA2  
PA1  
PA0  
A2**  
A1  
C000  
C001  
C002  
C003  
C004  
C005  
C006  
C007  
1
2
3
4
1
2
3
4
5
6
7
8
AD7824*  
AD7828*  
A0  
TMS32010  
MEN  
CS  
DEN  
RD  
D7  
DB7  
DATA BUS  
D0  
DB0  
MC68000 MICROPROCESSOR  
Figure 17 shows an MC68000 interface. The AD7824/AD7828  
is operating in Mode 0. Assume the ADC is again assigned a  
memory block starting at address C000. A MOVE instruction  
*
**  
LINEAR CIRCUITRY OMITTED FOR CLARITY.  
FORTHE AD7828 ONLY  
Figure 18. AD7824/AD7828–TMS32010 Interface  
REV. F  
–10–  
1...78910111213...16

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