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5962-8871903MYA

更新时间： 2024-02-23 02:53:13

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
23页	671K
描述
Monolithic 12-Bit Quad DAC

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5962-8871903MYA 数据手册

AD664

Table II. AD664 Digital Truth Table

Function

DS1, DS0

QS0, 1, 2¹

RST

Load 1st Rank (data)

DACA

DACB

DACC

DACD

Select Quad

1→0

Load 2nd Rank (data)

Readback 2nd Rank (data)

Reset

XXX

1→0

Select D/A

Select Quad

XXX

Transparent¹

All DACs

DACA

000

1→0

DACB

DACC

DACD

Mode Select^{1, 2}

1st Rank

2nd Rank

00X

XXX

1→0

Readback Mode¹

00X

1→0

Update 2nd Rank

and Mode

XXX

1→0

NOTES

X = Don’t Care.

¹For 44-pin versions only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.

²For MS, TR, LS = 0, a MS 1st write occurs.

The following sections detail the timing requirements for

various data loading schemes. All of the timing specifica-

tions shown assume V_IH= 2.4 V, V_IL= 0.4 V, V_CC= +15 V,

_EE= –15 V and V_LL= +5 V.

Load and Update One DAC Output

In this first example, the object is simply to change the output of

one of the four DACs on the AD664 chip. The procedure is to

select the address bits that indicate the DAC to be programmed,

pull LATCH SELECT (LS) low, pull CHIP SELECT (CS)

low, release LS and then release CS. When CS goes low, data

enters the first rank of the input latch. As soon as LS goes high,

the data is transferred into the second rank and produces the

new output voltage. During this transfer, MS, TR, RD and RST

should be held high.

Figure 9a. Update Output of a Single DAC

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_LS

Preloading the First Rank of One DAC

In this case, the object is to load new data into the first rank of

one of the DACs but not the output. As in the previous case, the

address and data inputs are placed on the appropriate pins. LS

is then brought to “0” and then CS is asserted. Note that in this

situation, however, CS goes high before LS goes high. The in-

put data is prevented from getting to the second rank and affect-

ing the output voltage.

t_DS

t_DH

t_LW

t_CH

t_AS

t_AH

*FOR t_LS> 0, THE WIDTH OF LS MUST BE

INCREASED BY THE SAME AMOUNT THAT

t_LSIS GREATER THAN 0 ns.

Figure 9b. Update Output of a Single DAC Timing

REV.

–8–

1...5 6 789 10 11...23

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