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5962-8865802XA PDF预览

5962-8865802XA

更新时间： 2024-02-03 13:27:32
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
12页 165K
描述
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP32, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-32, Analog to Digital Converter

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5962-8865802XA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：32
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.63
Is Samacsys：N最大模拟输入电压：10 V
最小模拟输入电压：-10 V转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-CDIP-T32JESD-609代码：e0
长度：41.15 mm模拟输入通道数量：1
位数：12功能数量：1
端子数量：32最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY, OFFSET BINARY, COMPLEMENTARY BINARY, 2'S COMPLEMENT BINARY, COMPLEMENTARY OFFSET BINARY
输出格式：SERIAL, PARALLEL, WORD封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：7.112 mm
表面贴装：NO温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15.24 mm
Base Number Matches：1

5962-8865802XA 数据手册

 浏览型号5962-8865802XA的Datasheet PDF文件第6页浏览型号5962-8865802XA的Datasheet PDF文件第7页浏览型号5962-8865802XA的Datasheet PDF文件第8页浏览型号5962-8865802XA的Datasheet PDF文件第10页浏览型号5962-8865802XA的Datasheet PDF文件第11页浏览型号5962-8865802XA的Datasheet PDF文件第12页 
AD578/AD579  
CLOCK RATE CONTROL  
J GRADE  
K,T GRADES  
The internal clock is preset to a nominal conversion time of 5.6 ms  
(AD578) or 4.8 ms (AD579). It can be adjusted for either faster  
or slower conversion rates. For faster conversions, connect the  
appropriate 1% resistor between Pins 17 and 18, and short  
Pin 18 to Pin 19. See Figures 6, 7, and 8.  
2.2␮s  
CONVERSION  
RATE  
1.8␮s  
CONVERSION  
RATE  
649⍀  
422⍀  
1%  
1%  
For slower conversions (AD578 only), connect a capacitor  
between Pins 15 and 17.  
Figure 8. AD579 Clock Rate Control Connection  
Note that the No Missing Code operation is not guaranteed  
when operating in this mode if a particular grade’s conversion  
speed specification is exceeded.  
Short Cycle Input—A short cycle input, Pin 14, permits the  
timing cycle to be terminated after any number of desired bits  
has been converted, allowing shorter conversion times in appli-  
cations not requiring the full 10-bit (AD579) or 12-bit (AD578)  
resolution. Short cycle pin connections and associated conver-  
sion times are summarized in Tables III and IV.  
3␮s  
CONVERSION  
RATE  
6␮s  
CONVERSION  
RATE  
4.5␮s  
CONVERSION  
RATE  
L GRADE  
K,T GRADES  
J, S GRADES  
TO SLOW  
CONVERSION,  
USE C  
FROM  
FIGURE 7  
Table III. AD578 Short Cycle Connections  
825⍀  
؎1%  
3.32⍀  
؎1%  
Resolution (Bits)  
12  
10  
8
Connect Pin 14 to Pin  
Conversion Speed (ms)  
16  
3
2
2.5  
4
2
Figure 6. AD578 Clock Rate Control Connection  
CAPACITANCE – pF  
1000  
680  
330  
Table IV. AD579 Short Cycle Connections  
13.0  
10.0  
8.0  
Resolution (Bits)  
10  
8
CAPACITOR  
RESISTOR  
Connect Pin 14 to Pin  
Conversion Speed (ms)  
2
1.8  
4
1.5  
External Clock—An external clock may be connected directly  
to the clock input, Pin 19. When operating in this mode, the  
convert start should be held high for a minimum of one clock  
period in order to reset the SAR and synchronize the conversion  
cycle. A positive-going pulsewidth of 100 ns to 200 ns will provide  
a continuous string of conversions that start on the first rising  
edge of the external clock after the EOC output has gone low.  
6.0  
4.0  
2.0  
1.5  
External Buffer Amplifier—In applications where the AD578 or  
AD579 is to be driven from high impedance sources or directly  
from an analog multiplexer, a fast slewing, wideband op amp like  
the AD711 should be used. See Figure 9.  
10k  
200  
2k  
RESISTANCE – ⍀  
Figure 7. AD578 Conversion Times vs. R or C Values  
V
V
GND  
SS  
DD  
+5V +15V –15V  
+V  
AD711  
–V  
OUT  
ANALOG INPUT  
0V–10V  
S1  
AD7506  
S16  
DATA BITS  
1–12  
A0 A1 A2 A3  
EN  
AD578  
OR  
AD579  
Figure 9. Input Buffer  
REV. B  
–9–  
1...6789101112

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