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5962-8755201RA PDF预览

5962-8755201RA

更新时间: 2024-01-15 11:47:38
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
22页 1186K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

5962-8755201RA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.01
控制类型:ENABLE LOW系列:AC
JESD-30 代码:R-GDIP-T20长度:24.51 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
Prop。Delay @ Nom-Sup:12.5 ns传播延迟(tpd):12.5 ns
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-8755201RA 数据手册

 浏览型号5962-8755201RA的Datasheet PDF文件第2页浏览型号5962-8755201RA的Datasheet PDF文件第3页浏览型号5962-8755201RA的Datasheet PDF文件第4页浏览型号5962-8755201RA的Datasheet PDF文件第6页浏览型号5962-8755201RA的Datasheet PDF文件第7页浏览型号5962-8755201RA的Datasheet PDF文件第8页 
SN54AC244, SN74AC244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS514E − JUNE 1995 − REVISED OCTOBER 2003  
switching characteristics over recommended operating free-air temperature range,  
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
T
A
= 25°C  
TYP  
5
SN54AC244  
SN74AC244  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
2.5  
2
MAX  
MIN  
1
MAX  
9.5  
9
MIN  
1
MAX  
7.5  
7.5  
8
t
t
t
t
t
t
7
7
7
8
9
9
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
Y
Y
Y
5
1
1
5
1
9
1.5  
1.5  
1
ns  
OE  
OE  
5.5  
6.5  
6.5  
1
10.5  
10.5  
11  
8.5  
9.5  
9.5  
1
ns  
1
2
operating characteristics, VCC = 5 V, TA = 25°C  
PARAMETER  
TEST CONDITIONS  
TYP  
UNIT  
C
Power dissipation capacitance per buffer/driver  
C = 50 pF,  
L
f = 1 MHz  
45  
pF  
pd  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
TEST  
/t  
S1  
S1  
Open  
500 Ω  
t
t
Open  
PLH PHL  
t
From Output  
Under Test  
/t  
2 × V  
PLZ PZL  
CC  
/t  
Open  
PHZ PZH  
C = 50 pF  
(see Note A)  
L
500 Ω  
Output  
Control  
(low-level  
enabling)  
V
LOAD CIRCUIT  
CC  
50% V  
50% V  
CC  
CC  
0 V  
t
t
PLZ  
PZL  
V
CC  
Input  
Output  
V  
CC  
50% V  
50% V  
CC  
CC  
Waveform 1  
50% V  
CC  
0 V  
V
V
+ 0.3 V  
− 0.3 V  
OL  
S1 at 2 × V  
CC  
V
OL  
t
PLH  
(see Note B)  
t
PHL  
t
t
PHZ  
PZH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
OH  
OH  
50% V  
50% V  
Output  
50% V  
CC  
CC  
CC  
V
OL  
0 V  
VOLTAGE WAVEFORMS  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 Ω, t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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