Datasheet > 5962-87539053X

5962-87539053X

更新时间： 2024-01-13 18:01:03

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟 ATM 异步传输模式输入元件可编程逻辑
页数	文件大小	规格书
13页	531K
描述
UV PLD, 15ns, CMOS, CQCC28, WINDOWED, CERAMIC, LCC-28

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技术参数
数据手册

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5962-87539053X 技术参数

生命周期：	Transferred	包装说明：	WQCCN,
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.26
Is Samacsys：	N	最大时钟频率：	50 MHz
JESD-30 代码：	S-CQCC-N28	长度：	11.4554 mm
专用输入次数：	11	I/O 线路数量：	10
端子数量：	28	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	11 DEDICATED INPUTS, 10 I/O
输出函数：	MACROCELL	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	WQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, WINDOW	可编程逻辑类型：	UV PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	2.79 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.4554 mm	Base Number Matches：	1

5962-87539053X 数据手册

AT22V10/L

Preload of Registered Outputs

The registers in the AT22V10 and AT22V10L are provided

with circuitry to allow loading of each register asynchro-

nously with either a high or a low. This feature will simplify

testing since any state can be forced into the registers to

Level forced on

registered output pin

during preload cycle

after cycle

control test sequencing. A V level on the I/O pin will

High

force the register high; a V will force it low, independent

Low

of the polarity bit (C0) setting. The preload state is entered

by placing an 11.5-V to 13-V signal on pin 8 on DIPs, and

pin 10 on SMPs. When the clock pin is pulsed high, the

data on the I/O pins is placed into the ten registers.

= 100 ns

DMIN

Power Up Reset

The registers in the AT22V10 and AT22V10L are de-

signed to reset during power up. At a point delayed slightly

from V

crossing 3.8 V, all registers will be reset to the

low state. The output state will depend on the polarity of

the output buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the un-

certainty of how V actually rises in the system, the fol-

lowing conditions are required:

1) The V rise must be monotonic,

Description

Parameter

Min Typ Max Units

2) After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and

Power-Up

Reset Time

600 1000

3) The clock must remain stable during t

1-103

1...4 5 678 9 10...13

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