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595CD10M0000DG PDF预览

595CD10M0000DG

更新时间: 2024-09-25 07:38:43
品牌 Logo 应用领域
芯科 - SILICON 机械振荡器
页数 文件大小 规格书
12页 313K
描述
CMOS Output Clock Oscillator

595CD10M0000DG 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.64其他特性:TRI-STATE; ENABLE/DISABLE FUNCTION; TRAY
最大控制电压:3.3 V最小控制电压:
频率调整-机械:NO频率偏移/牵引率:100 ppm
频率稳定性:20%JESD-609代码:e4
线性度:10%安装特点:SURFACE MOUNT
标称工作频率:10 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:CMOS
输出负载:15 pF物理尺寸:7.0mm x 5.0mm x 1.8mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
最大对称度:55/45 %端子面层:GOLD OVER NICKEL
Base Number Matches:1

595CD10M0000DG 数据手册

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Si595  
REVISION D  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 TO 810 MHZ  
Features  
Available with any-rate output  
frequencies from 10 to 810 MHz  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
®
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
Pb-free/RoHS-compliant  
–40 to +85 ºC operating range  
3rd generation DSPLL with  
superior jitter performance  
Internal fixed fundamental mode  
crystal frequency ensures high  
reliability and low aging  
Applications  
Ordering Information:  
See page 7.  
SONET/SDH (OC-3/12/48)  
Networking  
SD/HD SDI/3G SDI video  
FTTx  
Clock recovery and jitter cleanup PLLs  
FPGA/ASIC clock generation  
Pin Assignments:  
Description  
See page 6.  
®
The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si595 is available with  
any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs,  
where a different crystal is required for each output frequency, the Si595  
uses one fixed crystal to provide a wide range of output frequencies. This IC-  
based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides supply noise rejection, simplifying the task of generating low-jitter  
clocks in noisy environments. The Si595 IC-based VCXO is factory-  
configurable for a wide variety of user specifications including frequency,  
supply voltage, output format, tuning slope, and absolute pull range (APR).  
Specific configurations are factory programmed at time of shipment, thereby  
eliminating the long lead times associated with custom oscillators.  
(Top View)  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
CLK– CLK+  
VDD  
Any-rate  
10–810 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Rev. 1.2 4/13  
Copyright © 2013 by Silicon Laboratories  
Si595  

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