Datasheet > 595CD148M500DG

595CD148M500DG

更新时间： 2024-09-24 19:36:23

品牌	Logo	应用领域
芯科 - SILICON		振荡器
页数	文件大小	规格书
15页	295K
描述
CMOS Output Clock Oscillator, 10MHz Min, 160MHz Max, 148.5MHz Nom

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595CD148M500DG 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.62
JESD-609代码：	e4	安装特点：	SURFACE MOUNT
端子数量：	6	最大工作频率：	160 MHz
最小工作频率：	10 MHz	标称工作频率：	148.5 MHz
最高工作温度：	85 °C	最低工作温度：	-40 °C
振荡器类型：	CMOS	封装主体材料：	CERAMIC
封装等效代码：	DILCC6,.2	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Oscillators
最大压摆率：	100 mA	标称供电电压：	3.3 V
表面贴装：	YES	端子面层：	Gold (Au) - with Nickel (Ni) barrier
Base Number Matches：	1

595CD148M500DG 数据手册

Si595

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 TO 810 MHZ

Features



Available with any-rate output

frequencies from 10 to 810 MHz



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry standard 5x7 and

3.2x5 mm packages

Si5602



3rd generation DSPLL with

superior jitter performance

Internal fixed fundamental mode

crystal frequency ensures high

reliability and low aging



Pb-free/RoHS-compliant

–40 to +85 ºC operating range

Applications

Ordering Information:

See page 8.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video



FTTx

Clock recovery and jitter cleanup PLLs

FPGA/ASIC clock generation

Pin Assignments:

Description

See page 7.

The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si595 is available with

any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs,

where a different crystal is required for each output frequency, the Si595

uses one fixed crystal to provide a wide range of output frequencies. This IC-

based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides supply noise rejection, simplifying the task of generating low-jitter

clocks in noisy environments. The Si595 IC-based VCXO is factory-

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, tuning slope, and absolute pull range (APR).

Specific configurations are factory programmed at time of shipment, thereby

eliminating the long lead times associated with custom oscillators.

(Top View)

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10–810 MHz

DSPLL^®

Fixed

Frequency

Clock Synthesis

ADC

GND

Rev. 1.3 12/17

Si595

12 3 4 5 6 7...15

中文翻译

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595D105X_035A2T	VISHAY	获取价格	Solid Tantalum Chip Capacitors TANTAMOUNT® Co

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