Datasheet > 557MI-01LFT

557MI-01LFT

更新时间： 2024-01-18 19:50:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟 PC 光电二极管外围集成电路晶体
页数	文件大小	规格书
10页	121K
描述
PCI-EXPRESS GEN1 CLOCK SOURCE

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557MI-01LFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.29
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	湿度敏感等级：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	100 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Clock Generators	最大压摆率：	55 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

557MI-01LFT 数据手册

ICS557-01

PCI-EXPRESS GEN1 CLOCK SOURCE

PCIE

Applications Information

External Components

A minimum number of external components are required for

proper operation.

Output Structures

6*IREF

IREF

=2.3 mA

Decoupling Capacitors

Decoupling capacitors of 0.01 μF should be connected

between VDD and the ground plane (pin 4) as close to the

VDD pin as possible. Do not share ground vias between

components. Route power from power source through the

capacitor pad and then into IDT pin.

Crystal

See Output Termination

Sections - Pages 3 ~ 5

A 25 MHz fundamental mode parallel resonant crystal with

R_R475

C = 16 pF should be used. This crystal must have less than

300 ppm of error across temperature in order for the

ICS557-01 to meet PCI Express specifications.

General PCB Layout Recommendations

Crystal Capacitors

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Crystal capacitors are connected from pins X1 to ground

and X2 to ground to optimize the accuracy of the output

frequency.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

C = Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (C - 8) * 2

2. No vias should be used between decoupling capacitor

and VDD pin.

For example, for a crystal with a 16 pF load cap, each

external crystal cap would be 16 pF. (16-8)*2=16.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

Current Source (Iref) Reference Resistor - R

If board target trace impedance (Z) is 50Ω, then R = 475Ω

(1%), providing IREF of 2.32 mA. The output current (I ) is

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the ICS557-01.This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

equal to 6*IREF.

Output Termination

The PCI-Express differential clock outputs of the ICS557-01

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines section.

The ICS557-01can also be configured for LVDS compatible

voltage levels. See the LVDS Compatible Layout Guidelines

section

IDT® PCI-EXPRESS GEN1 CLOCK SOURCE

ICS557-01

REV P 072512

1 234 5 6 7...10

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与557MI-01LFT相关器件

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