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554BEXXXXXXBG

更新时间： 2022-09-22 00:02:58
品牌 Logo 应用领域
芯科 - SILICON 发射机
页数 文件大小 规格书
20页 296K
描述
SiPHY OC-192/STM-64 TRANSMITTER

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Si5540  
PRELIMINARY DATA SHEET  
SiPHY™ OC-192/STM-64 TRANSMITTER  
Features  
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated  
™
16:1 multiplexer and DSPLL based clock multiplier unit:  
Data Rates Supported: OC-192/STM-64,  
10GbE, and 10.7 Gbps FEC  
Low Power Operation 0.6 W (typ)  
Small Footprint: 99-Pin BGA Package  
(11 x 11 mm)  
OIF SFI-4 Compliant Interface  
Output Clock Powerdown  
Operates with 155 or 622 MHz  
Reference Sources  
Optional 3.3 V Supply Pin for  
LVTTL Compatible Outputs  
Single 1.8 V Supply Operation  
DSPLL™ Based Clock Multiplier Unit  
w/ selectable loop filter bandwidths  
Bottom View  
Applications  
Ordering Information:  
See page 17.  
Sonet/SDH/ATM Routers  
Add/Drop Multiplexers  
Digital Cross Connects  
Optical Transceiver Modules  
Sonet/SDH Test Equipment  
Description  
The Si5540 is a fully integrated low-power transmitter for high-speed serial  
communication systems. It combines high speed clock generation with a 16:1  
multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based  
™
on Silicon Laboratories’ DSPLL technology which eliminates the external loop  
filter components required by traditional clock multiplier units. In addition,  
selectable loop filter bandwidths are provided to ensure superior jitter performance  
while relaxing the jitter requirements on external clock distribution subsystems.  
Support for data streams up to 10.7 Gbps is also provided for applications that  
employ forward error correction (FEC).  
The Si5540 represents a new standard in low jitter, low power and small size for  
10 Gbps serial transmitters. It operates from a single 1.8 V supply over the  
industrial temperature range (–40°C to 85°C).  
Functional Block Diagram  
REFSEL  
2
REFCLK  
REFRATE  
TXCLK16IN  
DSPLLTM  
CMU  
TXLOL  
BWSEL  
2
16  
TXCLK16OUT  
TXCLK16IN  
÷
TXCLKDSBL  
TXCLKOUT  
2
2
2
32  
TXDIN[15:0]  
FIFORST  
TXDOUT  
Reset  
Control  
Bias  
FIFOERR  
TXMSBSEL  
REXT  
RESET  
TXSQLCH  
Preliminary Rev. 0.31 8/01  
Copyright © 2001 by Silicon Laboratories  
Si5540-DS031  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  
1234567...20

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