Datasheet > 550AC415M000DGR

550AC415M000DGR

更新时间： 2024-11-28 04:15:35

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
15页	1136K
描述
LVPECL Output Clock Oscillator,

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中文翻译

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数据手册

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550AC415M000DGR 数据手册

Si550

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features



Available with any frequency from

10 to 945 MHz and select

frequencies to 1.4 GHz



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Si5602



3rd generation DSPLL with

superior jitter performance (0.5 ps)

3x better temperature stability than

SAW-based oscillators



Excellent PSRR performance



Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 10.



SONET/SDH

xDSL

10 GbE LAN/WAN



Low-jitter clock generation

Optical modules

Clock and data recovery



Pin Assignments:

See page 9.

Description

(Top View)

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 supports any

frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike

traditional VCXOs, where a different crystal is required for each output

frequency, the Si550 uses one fixed crystal to provide a wide range of output

frequencies. This IC-based approach allows the crystal resonator to provide

exceptional frequency stability and reliability. In addition, DSPLL clock

synthesis provides superior supply noise rejection, simplifying the task of

generating low-jitter clocks in noisy environments typically found in

communication systems. The Si550 IC-based VCXO is factory-configurable

for a wide variety of user specifications, including frequency, supply voltage,

output format, tuning slope, and temperature stability. Specific configurations

are factory programmed at time of shipment, thereby eliminating the long

lead times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

V_DD

Any-Frequency

Fixed

Frequency

10 MHz–1.4 GHz

CLK+

CLK–

DSPLL^®

Clock Synthesis

ADC

GND

Rev. 1.2 6/18

Si550

12 3 4 5 6 7...15

中文翻译

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与550AC415M000DGR相关器件

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550AC74M2500DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 74.25MHz Nom
550AC74M2500DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 74.25MHz Nom
550AC800M000DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 800MHz Nom
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550AD1000M00DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 1000MHz Nom

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