Datasheet > 550AD1213M000GR

550AD1213M000GR

更新时间： 2023-01-03 10:58:10

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
8页	181K
描述
Oscillator

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数据手册

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550AD1213M000GR 数据手册

Si550

PRELIMINARY DATA SHEET

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

(10 MHZ TO 1.4 GHZ)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and selected frequencies to 1.4 GHz

Industry-standard 7x5 mm package

Available CMOS, LVPECL, & CML

outputs

3rd generation DSPLL with

superior jitter performance

Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602

Lead-free/RoHS-compliant

3x better frequency stability than

SAW based oscillators

Applications

Ordering Information:

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

See page 7.

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike a traditional VCXO, the crystal frequency inside the Si550

is fixed for a wide range of output frequencies. The control voltage is

digitized and used as a numerical input to the DSPLL clock synthesis

engine. This IC-based approach eliminates the varactor and its associated

noise and non-linear performance drawbacks, allowing the crystal resonator

to be optimized for superior frequency stability, reliability, and mechanical

integrity. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy

environments typically found in communication systems. The Si550 IC-

based VCXO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output, and tuning slope. Specific

configurations are factory programmed into the Si550 at time of shipment,

thereby eliminating the long lead times associated with custom oscillators.

Functional Block Diagram

CLK- CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL™

Clock

Fixed

Frequency

Synthesis

ADC

GND

Preliminary Rev. 0.2 8/05

Si550

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7 8

中文翻译

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与550AD1213M000GR相关器件

型号	品牌	获取价格	描述	数据表
550AD132M812DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 132.812MHz Nom
550AD132M812DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 132.812MHz Nom
550AD1417M000DG	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 1417MHz Nom
550AD1417M000DGR	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 1417MHz Nom
550AD155M250DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 155.25MHz Nom
550AD155M520DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 155.52MHz Nom
550AD155M520DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 155.52MHz Nom
550AD156M300DGR	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 156.3MHz Nom
550AD166M629DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 166.629MHz Nom
550AD167M332DG	SILICON	获取价格	Oscillator, 10MHz Min, 1417MHz Max, 167.332MHz Nom

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