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54F283FM

更新时间： 2024-01-17 12:46:31
品牌 Logo 应用领域
美国国家半导体 - NSC 运算电路逻辑集成电路
页数 文件大小 规格书
10页 186K
描述
4-Bit Binary Full Adder with Fast Carry

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中文翻译

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54F283FM 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：compliant风险等级：5.68
Is Samacsys：NBase Number Matches：1

54F283FM 数据手册

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Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
Output I /I  
HIGH/LOW  
OH OL  
b
20 mA/ 1.2 mA  
b
20 mA/ 1.2 mA  
b
20 mA/ 0.6 mA  
A –A  
0
A Operand Inputs  
B Operand Inputs  
Carry Input  
1.0/2.0  
1.0/2.0  
1.0/1.0  
50/33.3  
50/33.3  
3
3
B –B  
0
C
0
b
b
S –S  
0
Sum Outputs  
1 mA/20 mA  
1 mA/20 mA  
3
C
Carry Output  
4
Functional Description  
The ’F283 adds two 4-bit binary words (A plus B) plus the  
incoming Carry (C ). The binary sum appears on the Sum  
(S –S ) and outgoing carry (C ) outputs. The binary weight  
other means can be used to effectively insert a carry into, or  
bring a carry out from, an intermediate stage. Figure 2  
shows how to make a 3-bit adder. Tying the operand inputs  
0
0
3
4
of the various inputs and outputs is indicated by the sub-  
script numbers, representing powers of two.  
of the fourth adder (A , B ) LOW makes S dependent only  
3 3 3  
on, and equal to, the carry from the third adder. Using some-  
what the same principle, Figure 3 shows a way of dividing  
the ’F283 into a 2-bit and a 1-bit adder. The third stage  
adder (A , B , S ) is used merely as a means of getting a  
0
1
(A  
a
(A  
a
a
a
B )  
1
2
(A  
2
B
C )  
0
2
3
0
0
1
2
a
e
a
a
a
a
B )  
2
2
(A  
B )  
3
16C  
4
2
3
3
a
a
a
2
2
2
S
0
2S  
4S  
8S  
1
2
)
carry (C ) signal into the fourth stage (via A and B ) and  
10  
2
2
bringing out the carry from the second stage on S . Note  
a
e
Where (  
plus  
2
that as long as A and B are the same, whether HIGH or  
Interchanging inputs of equal weight does not affect the op-  
eration. Thus C , A , B can be arbitrarily assigned to pins  
2
2
0
0
0
LOW, they do not influence S . Similarly, when A and B  
2
2
2
5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.  
Due to the symmetry of the binary add function, the ’F283  
can be used either with all inputs and outputs active HIGH  
(positive logic) or with all inputs and outputs active LOW  
are the same the carry into the third stage does not influ-  
ence the carry out of the third stage. Figure 4 shows a meth-  
od of implementing a 5-input encoder, where the inputs are  
equally weighted. The outputs S , S and S present a bina-  
0
1
2
ry number equal to the number of inputs I –I that are true.  
(negative logic). See Figure 1. Note that if C is not used it  
0
must be tied LOW for active HIGH logic or tied HIGH for  
active LOW logic.  
1
5
Figure 5 shows one method of implementing a 5-input ma-  
jority gate. When three or more of the inputs I –I are true,  
the output M is true.  
1
5
Due to pin limitations, the intermediate carries of the ’F283  
are not brought out for use as inputs or outputs. However,  
5
C
A
0
A
A
2
A
B
0
B
1
B
2
B
3
S
0
S
1
S
2
S
C
4
0
1
3
3
Logic Levels  
L
L
H
L
H
H
L
L
H
H
H
L
L
H
Active HIGH  
Active LOW  
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
a
a
e
a
a
a
e
a
12 0  
Active HIGH: 0  
10  
9
3
16  
Active LOW: 1  
5
6
FIGURE 1. Active HIGH versus Active LOW Interpretation  
2
1234567...10

中文翻译

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54F283LLQB FAIRCHILD

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54F283LMQB ETC

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 		BINARY ADDER|F-TTL|LLCC|20PIN|CERAMIC
54F283M/B2AJC MOTOROLA

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54F298DM FAIRCHILD

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 		Multiplexer, F/FAST Series, 4-Func, 2 Line Input, 1 Line Output, True Output, TTL, CDIP16,
54F298DMQB FAIRCHILD

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 		Multiplexer, F/FAST Series, 4-Func, 2 Line Input, 1 Line Output, True Output, TTL, CDIP16,
54F298FM ETC

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 		2-Input Digital Multiplexer
54F298FMQB NSC

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 		F/FAST SERIES, NEGATIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16

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