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54ACT899QMX PDF预览

54ACT899QMX

更新时间: 2024-02-23 06:59:21
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
14页 207K
描述
9-Bit Latchable Transceiver with Parity Generator/Checker

54ACT899QMX 技术参数

生命周期:Obsolete包装说明:QCCN,
Reach Compliance Code:unknown风险等级:5.76
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列:ACTJESD-30 代码:S-CQCC-N28
长度:11.43 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:9功能数量:1
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:1.905 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:11.43 mmBase Number Matches:1

54ACT899QMX 数据手册

 浏览型号54ACT899QMX的Datasheet PDF文件第2页浏览型号54ACT899QMX的Datasheet PDF文件第3页浏览型号54ACT899QMX的Datasheet PDF文件第4页浏览型号54ACT899QMX的Datasheet PDF文件第5页浏览型号54ACT899QMX的Datasheet PDF文件第6页浏览型号54ACT899QMX的Datasheet PDF文件第7页 
August 1994  
74AC899 54ACT/74ACT899  
#
9-Bit Latchable Transceiver  
with Parity Generator/Checker  
General Description  
Features  
Y
Latchable transceiver with output sink of 24 mA  
The ’AC/’ACT899 is a 9-bit to 9-bit parity transceiver with  
transparent latches. The device can operate as a feed-  
through transceiver or it can generate/check parity from the  
8-bit data busses in either direction. The ’AC/’ACT899 fea-  
tures independent latch enables for the A-to-B direction and  
the B-to-A direction, a select pin for ODD/EVEN parity, and  
separate error signal output pins for checking parity.  
Y
Option to select generate parity and check or ‘‘feed-  
through’’ data/parity in directions A-to-B or B-to-A  
Independent latch enable for A-to-B and B-to-A direc-  
tions  
Y
Y
Y
Y
Y
Y
Select pin for ODD/EVEN parity  
ERRA and ERRB output pins for parity checking  
Ability to simultaneously generate and check parity  
May be used in system applications in place of the ’280  
May be used in system applications in place of the ’657  
and ’373 (no need to change T/R to check parity)  
4 kV minimum ESD immunity  
Y
Logic Symbol  
Connection Diagram  
Pin Assignment for PCC and LCC  
TL/F/10637–1  
TL/F/10637–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10637  
RRD-B30M75/Printed in U. S. A.  

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