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54ACT715D PDF预览

54ACT715D

更新时间: 2023-01-02 17:18:02
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德州仪器 - TI /
页数 文件大小 规格书
16页 323K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

54ACT715D 数据手册

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Signal Specification (Continued)  
DS100232-5  
FIGURE 2. Vertical Waveform Specification  
DS100232-12  
FIGURE 3. Equalization/Serration Interval Programming  
HORIZONTAL AND VERTICAL GATING SIGNALS  
Addressing Logic  
Horizontal Drive and Vertical Drive outputs can be utilized as  
general purpose Gating Signals. Horizontal and Vertical Gat-  
ing Signals are available for use when Composite Sync and  
Blank signals are selected and the value of Bit 2 of the Sta-  
tus Register is 0. The Vertical Gating signal will change in the  
same manner as that specified for the Vertical Blank.  
The register addressing logic is composed of two blocks of  
logic. The first is the address register and counter (AD-  
DRCNTR), and the second is the address decode (AD-  
DRDEC).  
ADDRCNTR LOGIC  
=
Horizontal Gating Signal Width  
[REG(16) − REG(15)] x  
ckper  
Addresses for the data registers can be generated by one of  
two methods. Manual addressing requires that each byte of  
each register that needs to be loaded needs to be ad-  
dressed. To load both bytes of all 19 registers would require  
a total of 57 load cycles (19 address and 38 data cycles).  
Auto Addressing requires that only the initial register value  
be specified. The Auto Load sequence would require only 39  
load cycles to completely program all registers (1 address  
and 38 data cycles). In the auto load sequence the low order  
byte of the data register will be written first followed by the  
high order byte on the next load cycle. At the time the High  
Byte is written the address counter is incremented by 1. The  
counter has been implemented to loop on the initial value  
loaded into the address register. For example: If a value of 0  
was written into the address register then the counter would  
count from 0 to 18 before resetting back to 0. If a value of 15  
was written into the address register then the counter would  
count from 15 to 18 before looping back to 15. If a value  
greater than or equal to 18 is placed into the address register  
the counter will continuously loop on this value. Auto ad-  
dressing is initiated on the falling edge of LOAD when AD-  
DRDATA is 0 and LHBYTE is 1. Incrementing and loading of  
data registers will not commence until the falling edge of  
LOAD after ADDRDATA goes to 1. The next rising edge of  
=
Vertical Gating Signal Width:  
[REG(18) − REG(17)] x  
hper  
CURSOR POSITION AND VERTICAL INTERRUPT  
The Cursor Position and Vertical Interrupt signal are avail-  
able when Composite Sync and Blank signals are selected  
and Bit 2 of the Status Register is set to the value of 1. The  
Cursor Position generates a single pulse of n clocks wide  
during every line that the cursor is specified. The signals are  
generated by logically ORing (ANDing) the active LOW  
(HIGH) signals specified by the registers used for generating  
Horizontal and Vertical Gating signals. The Vertical Interrupt  
signal generates a pulse during the vertical interval speci-  
fied. The Vertical Interrupt signal will change in the same  
manner as that specified for the Vertical Blanking signal.  
=
Horizontal Cursor Width [REG(16) − REG(15)] x ckper  
=
Vertical Cursor Width [REG(18) − REG(17)] x hper  
=
Vertical Interrupt Width [REG(14) − REG(13)] x hper  
5
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