Datasheet > 54ACT715D

54ACT715D

更新时间： 2023-01-02 17:18:02

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
16页	323K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

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中文翻译

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数据手册

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54ACT715D 数据手册

Addressing Logic (Continued)

LOAD will load the first byte of data. Auto Incrementing is

disabled on the falling edge of LOAD after ADDRDATA and

LHBYTE goes low.

Manual Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Load Address m

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Load Lbyte m

Load Hbyte m

Load Address n

Load Lbyte n

Load Hbyte n

DS100232-7

Auto Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Enable Auto Addressing

Load Start Address n

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Load Lbyte (n)

Load Hbyte (n); Inc Counter

Load Lbyte (n+1)

Load Hbyte (n+1); Inc Counter

Load Address

DS100232-8

ADDRDEC LOGIC

CLOCK is disabled. Clocking the part during a Vectored Re-

start or Vectored Clear state will have no effect on the part.

To resume operation in the new state, or disable the Vec-

tored Restart or Vectored Clear state, another

non-ADDRDEC address must be loaded. Operation will be-

gin in the new state on the rising edge of the non-ADDRDEC

load pulse. It is recommended that an unused address be

loaded following an ADDRDEC operation to prevent data

registers from accidentally being corrupted. The following

Addresses are used by the device.

The ADDRDEC logic decodes the current address and gen-

erates the enable signal for the appropriate register. The en-

able values for the registers and counters change on the fall-

ing edge of LOAD. Two types of ADDRDEC logic is enabled

by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-

start logic) and Addresses 23 or 55 (Vectored Clear logic).

Loading these addresses will enable the appropriate logic

and put the part into either a Restart (all counter registers are

reinitialized with preprogrammed data) or Clear (all registers

are cleared to zero) state. Reloading the same ADDRDEC

address will not cause any change in the state of the part.

The outputs during these states are frozen and the internal

Address 0

Status Register REG0

Address 1–18Data Registers REG1–REG18

www.national.com

1...3 4 567 8 9...16

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与54ACT715D相关器件

型号	品牌	获取价格	描述	数据表
54ACT715DM	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20
54ACT715DMQB	NSC	获取价格	IC SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20, Consumer IC:Other
54ACT715DMQB	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20
54ACT715L	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20
54ACT715LMQB	NSC	获取价格	IC SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20, Consumer IC:Other
54ACT715LMQB	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20
54ACT715P	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, PDIP20, PLASTIC, DIP-20
54ACT715-R	NSC	获取价格	Programmable Video Sync Generator
54ACT715-RD	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20
54ACT715-RDM	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

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