HORIZONTAL INTERVAL REGISTERS
Register Description (Continued)
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal
Sync and Blank pulses.
Bits 0–2
B2
B1
B0 VCBLANK VCSYNC HBLHDR HSYNVDR
REG1 — Horizontal Front Porch
0
0
0
CBLANK
CSYNC
HGATE
VGATE
REG2 — Horizontal Sync Pulse End Time
REG3 — Horizontal Blanking Width
(DEFAULT)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC
VSYNC
VSYNC
HBLANK
HGATE
VGATE
HSYNC
HSYNC
VINT
REG4 — Horizontal Interval Width
Line
#
of Clocks per
HBLANK
CSYNC CURSOR
CSYNC HBLANK
VSYNC CURSOR
VSYNC HBLANK
VERTICAL INTERVAL REGISTERS
VINT
The Vertical Interval Registers determine the number of lines
per frame, and the characteristics of the Vertical Blank and
Sync Pulses.
HSYNC
HSYNC
REG5 — Vertical Front Porch
REG6 — Vertical Sync Pulse End Time
REG7 — Vertical Blanking Width
Bits 3–4
B4
B3
Mode of Operation
Interlaced Double Serration and
REG8 — Vertical Interval Width
# of Lines per Frame
0
0
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
(DEFAULT) Equalization
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
These registers determine the width of equalization and ser-
ration pulses and the vertical interval over which they occur.
Non Interlaced Single Serration and
Equalization
REG 9 — Equalization Pulse Width End Time
REG10 — Serration Pulse Width End Time
REG11 — Equalization/Serration Pulse Vertical
Interval Start Time
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
REG12 — Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt
signal if used.
REG13 — Vertical Interrupt Activate Time
REG14 — Vertical Interrupt Deactivate Time
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value of
zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
B5 — VCBLANK Polarity
B6 — VCSYNC Polarity
B7 — HBLHDR Polarity
B8 — HSYNVDR Polarity
REG15 — Horizontal Cursor Position Start Time
REG16 — Horizontal Cursor Position End Time
REG17 — Vertical Cursor Position Start Time
REG18 — Vertical Cursor Position End Time
Bits 9–11
Bits 9 through 11 enable several different features of the de-
vice.
Signal Specification
B9 —
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
B10 — Disable System Clock (0)
Enable System Clock (1)
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
(see Figure 1). Since the first CLOCK edge, CLOCK #1,
causes the first falling edge of the Horizontal Blank reference
pulse, edges referenced to this first Horizontal edge are n +
1 CLOCKs away, where “n” is the width of the timing in ques-
tion. Registers 1, 2, and 3 are programmed in this manner.
The horizontal counters start at 1 and count until HMAX. The
value of HMAX must be divisible by 2. This limitation is im-
Default values for B10 are “0” in the ’ACT715/
LM1882 and “1” in the ’ACT715-R/LM1882-R.
B11 — Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.
3
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