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547BAA002422BAG PDF预览

547BAA002422BAG

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
16页 979K
描述
LVDS Output Clock Oscillator,

547BAA002422BAG 数据手册

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Ultra Series Crystal Oscillator  
Si547 Data Sheet  
Ultra Low Jitter Quad Any-Frequency XO (80 fs), 0.2 to 1500  
MHz  
KEY FEATURES  
• Available with any four selectable  
frequencies from 200 kHz to 1500 MHz  
The Si547 Ultra Seriesoscillator utilizes Silicon Laboratories’ advanced 4th gener-  
ation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at four  
selectable frequencies. The device is factory-programmed to provide any four se-  
lectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains ex-  
ceptionally low jitter for both integer and fractional frequencies across its operating  
range. The Si547 offers excellent reliability and frequency stability as well as guar-  
anteed aging performance. On-chip power supply filtering provides industry-leading  
power supply noise rejection, simplifying the task of generating low jitter clocks in  
noisy systems that use switched-mode power supplies. Offered in industry-standard  
3.2x5 mm and 5x7 mm footprints, the Si547 has a dramatically simplified supply  
chain that enables Silicon Labs to ship custom frequency samples 1-2 weeks after  
receipt of order. Unlike a traditional XO, where a different crystal is required for each  
output frequency, the Si547 uses one simple crystal and a DSPLL IC-based ap-  
proach to provide the desired output frequencies. This process also guarantees  
100% electrical testing of every device. The Si547 is factory-configurable for a wide  
variety of user specifications, including frequency, output format, and OE pin loca-  
tion/polarity. Specific configurations are factory-programmed at time of shipment,  
eliminating the long lead times associated with custom oscillators.  
• Ultra low jitter: 80 fs Typ RMS  
(12 kHz – 20 MHz)  
• Excellent PSRR and supply noise  
immunity: –80 dBc Typ  
• 7 ppm stability option (-40 to 85C)  
• 3.3 V, 2.5 V and 1.8 V V supply  
DD  
operation from the same part number  
• LVPECL, LVDS, CML, HCSL, CMOS, and  
Dual CMOS output options  
• 3.2×5, 5x7 mm package footprints  
• Samples available with 1-2 week lead times  
APPLICATIONS  
• 100G/200G/400G OTN, coherent optics  
• 10G/25G/40G/100G Ethernet  
Pin Assignments  
• 3G-SDI/12G-SDI/24G-SDI broadcast video  
FS1  
• Servers, switches, storage, NICs, search  
acceleration  
7
1
2
3
6
5
4
VDD  
CLK-  
CLK+  
OE/NC  
NC/OE  
GND  
• Test and measurement  
• Clock and data recovery  
• FPGA/ASIC clocking  
8
FS0  
(Top View)  
Pin #  
Descriptions  
Selectable via ordering option  
Fixed  
Frequency  
Crystal  
Frequency  
Flexible  
DSPLL  
1, 2  
Low  
Noise  
Driver  
OE = Output enable; NC = No Connect  
DCO  
Digital  
Phase  
Detector  
Digital  
Loop  
Filter  
3
4
5
6
7
8
GND = Ground  
OSC  
Phase Error  
Cancellation  
Flexible  
Formats,  
1.8V – 3.3V  
Operation  
CLK+ = Clock output  
Phase Error  
Fractional  
Divider  
CLK- = Complementary clock output. Not used for CMOS.  
VDD = Power supply  
NVM  
Control  
Power Supply Regulation  
FS1 = Frequency Select 1  
OE, Frequency Select  
(Pin Control)  
Built-in Power Supply  
Noise Rejection  
FS0 = Frequency Select 0  
silabs.com | Building a more connected world.  
Rev. 1.0  

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