Datasheet > 531FA150M000BGR

531FA150M000BGR

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
15页	265K
描述
LVDS Output Clock Oscillator, 150MHz Nom, 5 X 7 MM, ROHS COMPLIANT PACKAGE-6

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531FA150M000BGR 数据手册

Si530/531

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_OD

V_SE

swing (diff)

V_PP

—

swing (single-ended)

mid-level

0.5

—

0.93

LVDS Output Option

1.125

1.20

1.275

swing (diff)

V_OD

V_O

0.32

—

0.40

0.50

—

V_PP

CML Output Option

mid-level

– 0.75

V_OD

V_OH

V_OL

swing (diff)

0.70

0.8 x V_DD

—

0.95

—

1.20

V_DD

0.4

350

—

V_PP

CMOS Output Option

= 32 mA

I_OL= 32 mA

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

CMOS with CL = 15 pF

—

SYM

LVPECL:

LVDS:

– 1.3 V (diff)

—

1.25 V (diff)

CMOS:

Notes:

1. 50 Ω to V_DD– 2.0 V.

2. R_term= 100 Ω (differential).

3. C_L= 15 pF

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Phase Jitter (RMS)*

φ_J

12 kHz to 20 MHz (OC-48)

—

0.40

0.50

for F

> 500 MHz

OUT

50 kHz to 80 MHz (OC-192)

LVPECL

CML

LVDS

—

0.30

0.35

0.40

0.47

0.49

Phase Jitter (RMS)*

for F of 125 to 500 MHz

φ_J

12 kHz to 20 MHz (OC-48)

LVPECL

CML

LVDS

—

0.40

0.45

0.50

0.52

OUT

*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.

Rev. 1.0

1 234 5 6 7...15

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