Datasheet > 512NBA000874AAGR

512NBA000874AAGR

更新时间： 2024-02-24 03:06:36

品牌	Logo	应用领域
芯科 - SILICON		振荡器
页数	文件大小	规格书
23页	603K
描述
CMOS Output Clock Oscillator,

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技术参数
数据手册

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512NBA000874AAGR 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.71
振荡器类型：	CMOS	Base Number Matches：	1

512NBA000874AAGR 数据手册

浏览型号512NBA000874AAGR的Datasheet PDF文件第10页

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Si512/513

Table 6. Output Clock Jitter and Phase Noise (HCSL)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = HCSL

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Period Jitter

(RMS)

JPRMS

10k samples

—

1.2

Period Jitter

(Pk-Pk)

JPPKPK

φJ

10k samples

—

0.25

0.8

0.30

1.0

Phase Jitter

(RMS)

1.875 MHz to 20 MHz integration

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–90

–112

–120

–127

–140

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

*Note: Applies to an output frequency of 100 MHz.

Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = CMOS, Dual CMOS

Parameter

Phase Jitter

Symbol

Test Condition

Min

Typ

Max

Unit

φJ

1.875 MHz to 20 MHz integration

—

0.25

0.35

(RMS)

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

—

0.8

1.0

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–86

–108

–115

–123

–136

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

Rev. 1.2

1...5 6 789 10 11...23

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