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512KCA000230AAGR PDF预览

512KCA000230AAGR

更新时间: 2024-02-20 13:20:58
品牌 Logo 应用领域
芯科 - SILICON 振荡器
页数 文件大小 规格书
23页 603K
描述
CMOS Output Clock Oscillator,

512KCA000230AAGR 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.67
振荡器类型:CMOSBase Number Matches:1

512KCA000230AAGR 数据手册

 浏览型号512KCA000230AAGR的Datasheet PDF文件第14页浏览型号512KCA000230AAGR的Datasheet PDF文件第15页浏览型号512KCA000230AAGR的Datasheet PDF文件第16页浏览型号512KCA000230AAGR的Datasheet PDF文件第18页浏览型号512KCA000230AAGR的Datasheet PDF文件第19页浏览型号512KCA000230AAGR的Datasheet PDF文件第20页 
Si512/513  
8. PCB Land Pattern: 3.2 x 5.0 mm  
Figure 6 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si512/513. Table 18 lists the values for the  
dimensions shown in the illustration.  
Figure 6. Si512/513 Recommended PCB Land Pattern  
Table 18. PCB Land Pattern Dimensions (mm)  
Dimension  
(mm)  
2.60  
1.27  
0.80  
1.70  
C1  
E
X1  
Y1  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.  
3. This Land Pattern Design is based on the IPC-7351 guidelines.  
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material  
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.  
Solder Mask Design  
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the  
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.  
Stencil Design  
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be  
used to assure good solder paste release.  
7. The stencil thickness should be 0.125 mm (5 mils).  
8. The ratio of stencil aperture to land pad size should be 1:1.  
Card Assembly  
9. A No-Clean, Type-3 solder paste is recommended.  
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification  
for Small Body Components.  
Rev. 1.2  
17  
 
 

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