48SD6404RPFE

更新时间： 2024-01-22 05:23:52

品牌	Logo	应用领域
麦斯威 - MAXWELL		动态存储器
页数	文件大小	规格书
42页	595K
描述
256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks

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技术参数
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48SD6404RPFE 技术参数

生命周期：	Contact Manufacturer	零件包装代码：	DFP
包装说明：	DFP,	针数：	72
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.33
Is Samacsys：	N	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	6 ns	其他特性：	AUTO/SELF REFRESH
JESD-30 代码：	R-XDFP-F72	长度：	26.67 mm
内存密度：	268435456 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	4	功能数量：	1
端口数量：	1	端子数量：	72
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	64MX4
封装主体材料：	UNSPECIFIED	封装代码：	DFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
认证状态：	Not Qualified	座面最大高度：	4.16 mm
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	19 mm	Base Number Matches：	1

48SD6404RPFE 数据手册

48SD6404

256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM

Refresh

Auto-Refresh: All the banks must be precharged before executing an auto-refresh command. Since the

auto-refresh command updates the internal counter every time it is executed and determines the banks and

the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is

8192 cycles / 6.4ms. (8192 cycles are requires to refresh all the ROW addresses.) The output buffer

becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal

operation after the auto-refresh, an additional precharge operation by the precharge command is not

required.

Self-refresh¹: After executing a self-refresh command, the self-refresh operation continues while CKE is

held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A

self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-

refresh to all refresh addresses in or within 6.4 ms period on the condition (1) and (2) below.

(1) Enter self-refresh mode within 7.8 us after either burst refresh or distributed refresh at equal interval until

all refresh addresses are completed.

(2) Start burst refresh or distributed refresh at equal interval to all refresh addreses within 7.8 us after exiting

from self-refresh mode.

Others

Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In

power-down mode, power consumption is suppressed by deactivating the input initial circuit. Power-down

mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the

power-down mode, and command input is enabled from the next clock. In this mode, internal refresh is not

performed.

Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM

enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal

state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command

input is enabled from the next clock. For more details, refer to the “CKE Truth Table”.

Power-up sequence: The SDRAM should use the following sequence during power-up:

The CLK, CKE, CS, DQM and DQ pins stay low until power stabilizes.

The CLK pin is stable within 100ms after power stabilizes before the following initialization sequence.

The CKE and DQM is driven high between when power stabilizes and the initialization sequence.

This SDRAM has V clamp diodes for CLK, CKE, CS, DQM and DQ pins. If these pins go high before

power up, the large^Cc^Current flows from these pins to V through the diodes.

1. Self Refresh should only be used at temperatures below 70 °C

01.11.05 Rev 2

All data sheets are subject to change without notice 38

1...35 36 373839 40 41 42

中文翻译

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