Datasheet > 4305-00

4305-00

更新时间： 2022-09-19 10:45:21

品牌	Logo	应用领域
PSEMI		衰减器
页数	文件大小	规格书
11页	457K
描述
50 Ω RF Digital Attenuator 5-bit, 15.5 dB, DC - 4.0 GHz

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4305-00 数据手册

PE4305

Product Specification

Figure 15. Evaluation Board Layout

Evaluation Kit

The Digital Attenuator Evaluation Kit board was

designed to ease customer evaluation of the

PE4305 DSA.

J9 is used in conjunction with the supplied DC

cable to supply VDD, GND, and –VDD. If use of

the internal negative voltage generator is desired,

then connect –VDD (black banana plug) to

ground. If an external –VDD is desired, then apply

-3V.

J1 should be connected to the LPT1 port of a PC

with the supplied control cable. The evaluation

software is written to operate the DSA in serial

mode, so switch 7 (P/S) on the DIP switch SW1

should be ON with all other switches off. Using the

software, enable or disable each attenuation

setting to the desired combined attenuation. The

software automatically programs the DSA each

time an attenuation state is enabled or disabled.

To evaluate the Power Up options, first disconnect

the control cable from the evaluation board. The

control cable must be removed to prevent the PC

port from biasing the control pins.

During power up with P/S=1 high and LE=0 or P/

S=0 low and LE=1, the default power-up signal

attenuation is set to the value present on the five

control bits on the five parallel data inputs (C0.5 to

C8). This allows any one of the 32 attenuation

settings to be specified as the power-up state.

Figure 16. Evaluation Board Schematic

C0.5 C1

C2 C4

N/C

Z=50 Ohm

During power up with P/S=0 high and LE=0, the

control bits are automatically set to one of two

possible values presented through the PUP

interface. These two values are selected by the

power-up control bit, PUP2, as shown in Table 6.

RFin

RFout

QFN4X4

DATA

CLK

SMA

10 kohm

CLK

SMA

VNEG

GND

Pins 1 and 7 are open and may be connected to

any bias.

PUP2

VCC

Resistor on Pin 3

100 pF

A 10 kꢀ resistor on the input to pin 3 (Figure 16)

will eliminate package resonance between the RF

input pin and the digital input. Specified

Note: Resistor on pin 3 is required and should be placed as close to

the part as possible to avoid package resonance and meet error

specifications over frequency.

attenuation error versus frequency performance is

dependent upon this condition.

Document No. 70/0159~02C │ www.psemi.com

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