Datasheet > 39K165

39K165

更新时间： 2022-11-24 21:47:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
86页	1209K
描述
CPLDs at FPGA DensitiesTM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

39K165 数据手册

Delta39K™ ISR™

CPLD Family

Registered OE

Mux

OE Mux

From

Output PIM

Input

Mux

RES

To Routing

Channel

Mux

Output Mux

Bus

Hold

I/O

Mux

Clock

Polarity

Mux

Slew

Rate

RES

Control

Clock Mux

Mux

Figure 8. Block Diagram of I/O Cell

Table 3.

I/O Signals

There are four dedicated inputs (GCTL[3:0]) that are used as

Global I/O Control Signals available to every I/O cell. These

global I/O control signals may be used as output enables,

Figure 8. These global control signals, driven from four

dedicated pins, can only be used as active-high signals and

are available only to the I/O cells thereby implementing fast

resets, register and output enables.

I/O Standards

I/O

Termination

Standard

_REF(V)

Max.

V_CCIO

Voltage (V_TT)

Min.

LVTTL

LVCMOS

LVCMOS3

LVCMOS2

LVCMOS18

3.3V PCI

GTL+

N/A

3.3V

3.0V

2.5V

1.8V

3.3V

N/A

1.5

In addition, there are six OCC signals available to each I/O

cell. These control signals may be used as output enables,

Figure 8. Unlike global control signals, these OCC signal can

be driven from internal logic or and I/O pin.

One of the four global clocks can be selected as the clock for

the I/O cell register. The clock mux output is an input to a clock

polarity mux that allows the input/output register to be clocked

on either edge of the clock

0.9

1.3

1.1

1.7

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

3.3V

2.5V

1.5V

1.5

1.3

1.7

1.5

1.15

0.68

1.35

0.9

1.25

0.75

1.5

Slew Rate Control

The output buffer has a slew rate control option. This allows

the output buffer to slew at a fast rate (3 V/ns) or a slow rate

(1 V/ns). All I/Os default to fast slew rate. For designs

concerned with meeting FCC emissions standards the slow

edge provides for lower system noise. For designs requiring

very high performance the fast edge rate provides maximum

system performance.

HSTL II

0.9

HSTL III

HSTL IV

0.9

1.5

Document #: 38-03039 Rev. *H

Page 10 of 86

1...7 8 91011 12 13...86

下载PDF

与39K165相关器件

型号	品牌	描述	获取价格	数据表
39K1A205	CONEC	Protective Cover Assembly Kit Industrial Ethernet Connector (IP67) RoHS compliant	获取价格
39K1A364	CONEC	IP67 USB USB 2.0 Type A Plug Assembly Kit Solder Cup Version	获取价格
39K200	CYPRESS	CPLDs at FPGA DensitiesTM	获取价格
39K30	CYPRESS	CPLDs at FPGA DensitiesTM	获取价格
39K50	CYPRESS	CPLDs at FPGA DensitiesTM	获取价格
39LA-1PB-103	BOURNS	Potentiometer, Conductive Plastic, 0.25W, 10000ohm, 20% +/-Tol	获取价格