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3652 PDF预览

3652

更新时间: 2024-02-06 07:05:39
品牌 Logo 应用领域
德州仪器 - TI 隔离放大器分离技术隔离技术
页数 文件大小 规格书
14页 149K
描述
Optically-Coupled Linear ISOLATION AMPLIFIERS

3652 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIP-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.69Is Samacsys:N
放大器类型:ISOLATION AMPLIFIER最大共模电压:2000 V
最小绝缘电压:2000 VJESD-30 代码:R-MDMA-P32
标称负供电电压 (Vsup):-15 V功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:封装主体材料:METAL
封装代码:DIP封装等效代码:DIP32,.9
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED电源:+-8/+-18 V
认证状态:Not Qualified子类别:Isolation Amplifier
标称供电电压 (Vsup):15 V表面贴装:NO
温度等级:OTHER端子形式:PIN/PEG
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

3652 数据手册

 浏览型号3652的Datasheet PDF文件第5页浏览型号3652的Datasheet PDF文件第6页浏览型号3652的Datasheet PDF文件第7页浏览型号3652的Datasheet PDF文件第9页浏览型号3652的Datasheet PDF文件第10页浏览型号3652的Datasheet PDF文件第11页 
Model 722 DC/DC  
converter or equivalent  
I1  
11  
10  
+
C
P+  
722  
V+  
E
V–  
+VO  
–VO  
14  
+V  
(!)  
1.3kΩ  
23  
RIN  
C
13  
+
–V  
+
17  
+15VDC  
I2  
26  
VOUT  
–15VDC  
23  
+VCC  
20  
C
–VCC  
RIN  
12  
17  
C
Output  
29  
32 Bal  
10k(1)  
Output  
Common  
Bal  
VISO  
12  
16  
C
15  
50k(1)  
NOTE: (1) Optional Offset Adjust.  
V
OUT = (I1 – I2) X 106V/A + VISO X IMRR(2)  
3M(1)  
NOTE: (1) The offset adjustment circutry and power supply connections  
have been omitted for simplicity. Refer to Figure 5 for details. (2) IMRR  
here is in pA/V, typically 5pA/V at 60Hz and 1pA/V at DC.  
FIGURE 5. Power and Offset Adjust Connections.  
FIGURE 6a. 3650 with Differential Current Sources.  
INPUT CONFIGURATIONS  
Some possible input configurations for the 3650 and 3652  
are shown in Figures 6a, 6b, 6c. Differential input sources  
are used in these examples. For situations with nondifferential  
inputs, the appropriate source term should be set to zero in  
the gain equations and replaced with a short in the diagrams.  
V1  
RG1  
11  
10  
+
(1)  
Figure 6a shows the 3650 connected as a transconductance  
amplifier with input current sources. Voltage sources are  
shown in Figure 6b. In this case the voltages are converted  
to currents by RG1 and RG2. As shown by the equations, they  
perform as gain setting resistors in the voltage transfer  
function. When a single voltage source is used, it is recom-  
mended (but not essential) that the gain setting resistor  
remain split into two equal halves in order to minimize  
errors due to bias currents and common-mode rejection (see  
Typical Performance Curves).  
23  
RIN  
C
+
V2  
17  
RG2  
VOUT  
C
12  
VISO  
Figure 6c illustrates the connections for the 3652 when the  
FET buffer amplifiers, A1 and A2, are used. This configura-  
tion provides an isolation amplifier with high input imped-  
ance (both common-mode and differential, and good com-  
mon-mode and isolation-mode rejection. It is a true isolated  
instrumentation amplifier which has many benefits for noise  
rejection when source impedance imbalances are present.  
VISO  
106Ω  
RG1 + RG2 + RIN + RO  
VOUT = (V1 – V2) +  
IMRR  
NOTE: (1) The offset adjustment circutry and power supply connections  
have been omitted for simplicity. Refer to Figure 5 for details.  
FIGURE 6b. 3650 with Differential Voltage Sources.  
In the 3652, the voltage gain of the buffer amplifiers is  
slightly less than unity, but the gain of the output stage has  
been raised to compensate for this so that the overall transfer  
function from the ±I or ±IR inputs to the output is correct. It  
should be noted that A1 and A2 are buffer amplifiers. No  
summing can be done at the ±I or ±IR inputs. Figure 6c  
shows the +I and –I inputs used. If more input voltage  
protection is desired, then the +IR and –IR inputs should be  
used. This will increase the input noise due to the contribu-  
tion from the 1.6Mresistors, but will provide additional  
differential and common-mode protection (10ms rating of  
3kV).  
ERROR ANALYSIS  
A model of the 3650 suitable for DC error analysis of offset  
voltage, voltage drift versus temperature, bias current, etc.,  
is shown in Figure 7.  
A1 and A2, the input and output stage amplifiers, are consid-  
ered to be ideal. Separate external generators are used to  
model the offset voltages and bias currents. RIN is assumed  
to be small relative to RG1 and RG2 and is therefore omitted  
from the gain equation. The feedback configuration, optics  
and component matching are such that I1 = I2 = I3 = I4. A  
simple circuit analysis gives the following expression for the  
®
8
3650/52  

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