Datasheet > 33991

33991

更新时间： 2022-11-25 18:13:49

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动器仪表
页数	文件大小	规格书
36页	661K
描述
Gauge Driver Integrated Circuit

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33991 数据手册

Freescale Semiconductor, Inc.

STATIC ELECTRICAL CHARACTERISTICS

(Characteristics noted under conditions 4.75 V < V < 5.25 V, -40° C < TJ < 150° C, unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

SPI Timing Interface

Recommended Frequency of SPI Operation

—

167

MHz

µs

SPI

Falling edge of CS to Rising Edge of SCLK Required Setup Time) (Note9)

Falling edge of SCLK to Rising Edge of CS (Required Setup Time)(Note9)

SI to Falling Edge of SCLK (Required Setup Time) (Note9)

Falling Edge of SCLK to SI (Required Hold Time) (Note9)

SO Rise Time (CL = 200 pF)

—

LEAD

LAG

LSU

TSI

(HOLD)

SO Fall Time (CL = 200 pF)

SI, CS, SCLK, Incoming Signal Rise Time (Note10)

SI, CS, SCLK, Incoming Signal Fall Time (Note10)

Falling Edge of RST to Rising Edge of RST (Required Setup Time) (Note9)

RST

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note9)

(Note11)

—

µs

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note9)

Time from Falling Edge of CS to SO Low Impedance (Note12)

Time from Rising Edge of CS to SO High Impedance (Note13)

—

145

µs

SO(EN)

1.3

SO(DIS)

Time from Rising Edge of SCLK to SO Data Valid (Note14) 0.2 V < = SO

—

105

VALID

> = 0.8 V , CL = 200 pF

Notes:

9. The maximum setup times specified for the 33991 is the minimum time needed from the microcontroller to guarantee correct operation.

10. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

11. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.

12. Time required for output status data to be available for use at SO. 1 K Ω load on SO.

13. Time required for output status data to be terminated at SO. 1 K Ω load on SO.

14. Time required to obtain valid data out from SO following the rise of SCLK.

The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range specified in the

environmental requirements section. Digital Interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The

device shall be fully functional for slower clock speeds.

33991

^{MOTOROLA ANALOG INTEGRATED CIR}F^Co^UIr^TM^DEo^Vr^ICe^EI^Dn^Af^To^Armation On This Product,

Go to: www.freescale.com

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与33991相关器件

型号	品牌	获取价格	描述	数据表
33993	FREESCALE	获取价格	Multiple Switch Detection Interface
33996	FREESCALE	获取价格	16-Output Switch with SPI Control
339960	GENERAL	获取价格	INSTRUMENTATION CABLE
3399-6000	3M	获取价格	3M Pak 100 Wiremount Socket
3399-6006	3M	获取价格	26 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET, ROHS COMPLIANT
3399-6026	3M	获取价格	26 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET, ROHS COMPLIANT
3399-6050	3M	获取价格	3Mâ¢ Pak 100 Wiremount Socket
3399-60E	3M	获取价格	3Mâ¢ Pak 100 Wiremount Socket
3399-60I	3M	获取价格	3Mâ¢ Pak 100 Wiremount Socket
3399-60XX	3M	获取价格	3M Pak 100 Wiremount Socket

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