Datasheet > 3239-00

3239-00

更新时间： 2022-09-18 15:26:25

品牌	Logo	应用领域
PSEMI		/
页数	文件大小	规格书
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描述
2.2 GHz Integer-N PLL for Low Phase Noise Applications

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3239-00 数据手册

PE3239

Product Specification

Figure 2. Pin Configuration (Top View)

Figure 3. Package Type

20-lead TSSOP

V_DD

Enh

f_r

GND

N/C

S_WR

Sdata

Sclk

V_DD

Dout

GND

FSELS

E_WR

V_DD

Cext

GND

F_in

Table 1. Pin Descriptions

Pin No. Pin Name

Type

Description

V_DD

(Note 1)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.

Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ

pull-up resistor.

Enh

Input

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are

transferred to the secondary register on S_WR rising edge.

S_WR

Sdata

Sclk

Input

Binary serial data input. Input data entered MSB first.

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit

enhancement register (E_WR “high”) on the rising edge of Sclk.

GND

Ground.

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal

counters. Internal 70 kΩ pull-down resistor.

FSELS

Input

Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the

enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.

E_WR

V_DD

F_in

(Note 1)

Input

Same as pin 1.

Prescaler input from the VCO. Max frequency input is 2.2 GHz.

Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be

connected in series with a 50 Ω resistor to the ground plane.

F_in

Input

GND

Cext

Ground.

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to

an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.

Output

Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,

otherwise LD is a logic low (“0”).

Dout

V_DD

Output

Data out function, Dout, enabled in enhancement mode.

Same as pin 1.

(Note 1)

Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions

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