ISL8225MEVAL4Z Board Schematic
1 VOUT2
VOUT1 1
J1
2
4
J4
C9
4
2
C8
P1
P5
C11
C12
1000PF
E
1000PF
VOUT2
BA1
VOUT1
OPEN
E
R20
R22
OPEN
BA5
R3
R1
0
0
1K
1K
P2
P6
GND
GND
R9
R10
BA2
BA6
R14
DNP
R21
0
0
IN
IN
VCC
VCC
DNP
E
E
COMP1
OUT
VOUT2
VOUT1
2
3
4
5
6
7
20
19
18
17
16
15
COMP1
COMP2
MODE
OUT
OUT
COMP2
ISHARE
MODE
SYNC
ISHARE
VMON1
CLKOUT
EN/FF2
EN/FF1
OUT
OUT
IN
VMON2
SYNC
VMON2
VMON1
1
2
J2
U1
5
CLKOUT
EN/FF2
EN/FF1
RFSET
**
SGND
OUT
VCC
D
C1
4.7UF
ISL8225MIRZ
D
DNP
P7
VCC
IN
D
P3
VIN2
OUT
D
8
VIN1
D
VIN1
E
14
13
BA7
VIN2
BA3
CLKOUT
IN
CLKOUT
BA8
1
PHASE2
J5
PHASE1
9
2
5
P4
GND
P8
GND
D
BA4
E
E
R11
E
E
D
D
3.32K
PHASE2
PHASE1
R12
IN
VMON1
VCC
3.32K
IN
2
1
OUT
EN/FF1
JP1
ENC
LED1
OUT
EN/FF2
SSL_LXA3025IGC
VMON2
IN
IN
PGOOD
Q1
1
R18
D
2N7002-7-F
VIN2
IN
VIN1
IN
DNP
R19
D
D
E
COMP1
IN
DNP
DRAWN BY:
DATE:
08/04/2011
DATE:
ENGINEER:
JIAN YIN
TITLE:
DATE:
TIM KLEMANN
RELEASED BY:
COMP2
NOTE:
ISL8225M
EVALUATION BOARD
SCHEMATIC
**
IN
UPDATED BY:
STEVEN MCGEE
DATE:
10/26/2012
GROUND AND
D
GROUND ARE TIED TOGETHER AT PIN 6 OF U1.
E
TESTER
MASK#
HRDWR ID
ISL8225MEVAL4Z
REV.
D
FILENAME:
SHEET
D
OF
~/ISL8225M/ISL8225MEVAL4ZD
1
1
FIGURE 2. ISL8225MEVAL4Z BOARD SCHEMATIC