Datasheet > 31-5329-52RFX

31-5329-52RFX

更新时间： 2022-06-07 05:04:08

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英特矽尔 - INTERSIL		/
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描述
ISL8225MEVAL4Z Dual 15A/Optional 30A Cascadable Evaluation Board Setup Procedure

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31-5329-52RFX 数据手册

Application Note 1793

TABLE 3. ISL8225M OPERATION MODES

1ST MODULE (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BI-DIRECTION)

VMON1

MODES OF OPERATION

OPERATION OPERATION

OUTPUT

(SEE

DESCRIPTION

FOR DETAILS)

CLKOUT/REFIN

WRT 1^ST

OF 2^ND2^NDCHANNEL

VMON2 MODULE WRT 1^ST(O)

MODE

OF 2^ND

MODE

OF 3^RD

EN1/FF1 EN2/FF2 VSEN2- MODE VSEN2+

MODE

(I)

(I OR O)

(Note 2) (Note 2)

(NOTE 1)

MODULE

Disabled

Active Active Active

Active

VMON1 =

VMON2toKeep

PGOOD Valid

Single Phase

VMON1 =

VMON2toKeep

PGOOD Valid

Single Phase

<V_CC-0.7V Active Active 29% to 45%

of V_CC(I)

Active

0°

Dual Regulator

<V_CC-0.7V Active Active 45% to 62%

of V_CC(I)

90°

<V_CC-0.7V Active Active >62% of V_CC(I) Active

<V_CC-0.7V Active Active <29% of V_CC(I) Active

180°

-60°

Dual Regulator

DDR Mode

2-Phase

V_CC

GND

60°

VMON1

180°

Divider

V_CC

GND

60°

Divider Divider

180°

6-Phase

VMON1 Active

3 Outputs

Divider

V_CC

GND

V_CC

120°

90°

1kΩ

Active

Divider

Active

240°

180°

3-Phase

4-Phase

V_CC

90°

2 Outputs

(1^stmodule in

Mode 7A)

V_CC

90°

1kΩ

Active

180°

3, 4

3 Outputs

(1^stmodule in

Mode 7A)

Cascaded Module Operation MODEs 5B+5B+7A+5B+5B+5B/7A, No External Clock Required

External Clock or External Logic Circuits Required for Equal Phase Interval

12-Phase

5, 7, 8, 9, 10, 11,

(PHASE >12)

NOTE:

1. “2^NDCHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this

column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°.

2. “VMON1” means that the pin is tied to the VMON1 pin of the same module.

“Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 24 in the ISL8225M datasheet.

“1kΩ” means that there is a 1kΩ resistor connecting the pin to SGND; refer to Figure 22 in the ISL8225M datasheet.

AN1793.1

December 6, 2012

1 2 345 6 7...9

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