Index (Continued)
PCI Command (04h-05h)
PCI Control Function 1 (40h)
PCI Control Function 2 (41h)
Register
Revision Identification (08h)
Translation Type Bits 1
0
157
157
157
156
157
Power, Ground, No Connect Signals
Ground (VSS)
32
32
32
32
32
87
86
86
212
212
212
212
212
38
38
87
86
86
No Connect (NC)
Power Connect (VCC2)
Power Connect (VCC3)
Voltage Detect(VOLDET)
Privilege Level Transfers
Privilege Levels (CPL, DPL and RPL)
Privilege Levels (I/O)
Processor Core Instruction Set
Clock Counts
156
157
156
155
155
155
155
156
155
155
155
162
164
Vendor Identification (00h-01h)
PCI Configuration Registers 0CF8h-0CFBh
PCI Controller
CONFIG_ADDRESS
Configuration Cycles
PCI Arbiter
Space Control Registers
Special Cycles
Flags
Legend
Opcodes
Processor Initialization
Programming Interface
Protected Mode, Initialization and Transition
Protection
Current Privilege Level (CPL)
Descriptor Privilege Level (DPL)
Requested Privilege Level (RPL)
Protection - V86 Mode
X-Bus PCI Master
X-Bus PCI Slave
PCI Cycles
PCI Halt Command
PCI Interface Signals
Frame
86
86
88
27
27
Initiator Ready
Lock Operation
28
26
26
26
R
Multiplexed Address and Data
Multiplexed Command and Byte Enables
Parity
Register Controls
Register Sets
38
40
Application
Parity Error
28
Flags Register
General Purpose Register
Instruction Pointer Register
Segment Registers
Flags Register
General Purpose
Data Registers
Pointer and Index Registers
Instruction Pointer
Selection Rules
Model Specific Register
System Register Set
Registers
40
40
40
40
43
40
40
40
42
42
Request Lines
Target Ready
Target Stop
28
27
27
162
162
164
163
50
PCI Local Bus Specification
PCI Read Transactions
PCI Special Cycle Command
PCI Write Transactions
PCR Performance Control Register Index 20h
PERR
Pixel Arrangement Within a DWORD
Pointer and Index Registers
ECX Counter
28
135
40, 4404
40
40
40
40
40
182
174
174
174
174
176
175
179
EDI Destination Pointer
ESI Source Pointer
ESP Register
Application Register
Model Specific Register
REQ
40
59
28
38
166
PUSH and POP Instructions
Power and Ground Connections and Decoupling
Power Management
RESET
ROP (raster operation)
Row Address Strobe
CAS
3-Volt Suspend Mode
Advanced Power Management (APM)
CPU Suspend Command Registers
Initiating Suspend with HALT
Initiating Suspend with SUSP
Processor Serial Bus
29
29
29
29
29
29
CKE
RAS
RASA
RASB
WE
Responding to a PCI Access During Suspend Mode 177
Serial Packet Transmission
Stopping the Input Clock
Suspend Mode and Bus Cycles
Suspend Modulation
179
178
175
174
179
179
179
179
179
S
Scratchpad
2KB configurations
3KB configurations
SMM information
Scratchpad RAM
SDRAM Clocks
SDCLK_IN
97
97
97
97
Power Management Registers
PM_BASE (FFFF FF6Ch)
PM_CNTRL_CSTP (8508h-850Bh)
PM_CNTRL_TEN (8504h-8507h)
PM_MASK (FFFF FF7Ch)
PM_SER_PACK (850Ch-850Fh)
PM_STAT_SMI (8500h-8503h)
Power Planes
30
30
42
42
SDCLK_OUT
179
179
Segment Register Selection Rules
Segment Registers
Serial Packet
36–37
Power, Ground, No Connect
Ground (VSS)
CX5520
25
32
Revision 3.1
241
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