EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
2
Functional description
2.1
Block diagram
A simplified functional block diagram for EiceDRIVER™ 2EDR8259H, 2EDRx259X is given in Figure 3.
NC
7
1
UVLO
16
15
VDDA
INA
VDDI
VDDA
RX
TX
OUTA
GNDA
Active
Clamping
3,8
5
UVLO
14
11
Dead
Time
Control
Channel to Channel Isolation
DISABLE
UVLO
VDDB
INB
2
6
VDDB
10
9
RX
TX
OUTB
GNDB
STP/DTC
Active
Clamping
4
GNDI
Figure 3
Block diagram
2.2
Power supply and Undervoltage Lockout (UVLO)
Due to the input-to-output and channel-to-channel isolation, three power domains with independent power
management are required. Undervoltage Lockout (UVLO) functions for both input and output supplies ensure a
defined startup and robust functionality under all operating conditions.
2.2.1
Input supply voltage
The input die is powered via VDDI and supports a wide supply voltage range from 3 V to 17 V. A ceramic bypass
capacitor must be placed between VDDI and GNDI in close proximity to the device; a minimum bypass
capacitance of 100 nF is recommended.
Power consumption to some extent, depends on switching frequency, as the input signal is converted into a
train of repetitive current pulses to drive the coreless transformer. Due to the chosen robust encoding scheme
the average repetition rate of these pulses and thus the average supply current depends on the switching
frequency, fsw. However, for fsw < 500 kHz this effect is very small.
The Undervoltage Lockout function for the input supply VDDI ensures that, as long as VDDI is below UVLO (e.g. in
startup), no data is transferred to the output side and the gate driver output is held low (safety Lock-down at
startup). When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output
side is ready (not in UVLO condition), the output reacts according to the logic input.
2.2.2
Output supply voltage
The two output dies are powered via two independent supply voltages VDDA and VDDB (up to 20 V).
Two ceramic bypass capacitors must be placed between VDDA and GNDA and between VDDB and GNDB in close
proximity to the device. A minimum capacitance of 20 x Ciss (MOSFET input capacitance) is recommended to
ensure an acceptable ripple (5% of VDDO) on the supply pin.
The minimum supply voltage is set by the Undervoltage Lockout (UVLO) function. The gate driver output can be
switched only if the output supply voltage (VDDA, VDDB) exceeds the output-side UVLO. Thus, it can be
guaranteed that the switch transistor is not operated if the driving voltage is too low to achieve a complete and
fast transition to the "on" state. Low driving voltage, in fact, could cause the power MOSFET to enter its
saturation (ohmic) region with potentially destructive power dissipation; the output UVLO ensures that the
Datasheet
5
Rev. 1.4
2023-10-30
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