EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
Table 7
(continued) Logic for STP/DTC pin connected to GNDI via resistance RDTC
Condition
STP/DTC logic
E, F
The shoot-through protection pulls down the outputs OUTA, OUTB until one of the
outputs goes low. At this point, afer the configured driver dead-time, the other
output is allowed to go high
2.5
Gate driver outputs
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 5 A
sourcing and 9 A sinking peak current. The low on-resistance coming together with high driving current is
particularly beneficial for fast switching of very large MOSFETs. With a Ron of ∼1 Ω for the sourcing pMOS and
∼0.5 Ω for the sinking nMOS transistor the driver can in most applications be considered as a nearly ideal
switch. The p-channel sourcing transistor enables real rail-to-rail behavior without suffering from the voltage
drop unavoidably associated with nMOS source follower stages.
In case of floating inputs or insufficient supply voltage not exceeding the UVLO thresholds, the driver outputs
are actively clamped to the "low" level (GNDA, GNDB).
2.6
Fast active output clamping in UVLO conditions
The Undervoltage Lockout (UVLO) ensures that the gate driver output is not operated if the supplies are below
the UVLO thresholds. However, this is not sufficient to guarantee that the output of the driver is kept low.
Transients or noise in the power stage may pull-up the output node of the driver and the gate voltage causing
an unwanted turn-on of the switch; this is particularly critical in system using bootstrapping since, during start-
up, the supply of the high-side channel is delayed, while the low-side MOSFET is already switching. In resonant
topologies (as LLC), the half-bridge switching node may be pulled up afer the turn-off of the low-side switch.
When the low-side MOSFET is turned on again, the high-side gate voltage increase induced by dV/dt event
cannot be clamped by the driver RDSON,sink if the bootstrap supply is not yet available.
With a fast output clamping circuit in the output stage, the driver ensures safe operation against output
induced overshoots in all UVLO situations. This structure allows fast reaction and effective clamping of the
output pins (OUTA, OUTB). The exact reaction time depends on the output supply (VDDA, VDDB) and on the
output voltage levels; however, already for very low supply levels (~1 V), the active output clamp is able to react
in some tens of ns.
Undervoltage Lockout together with the output active clamping ensures that the outputs are actively held low
in case of insufficient supply voltages.
Table 8
Logic table in case of insufficient bias power - INA, INB, DISABLE
Inputs
DIS
Supplies
Outputs
INA INB
VDD
VDDA
VDDB
OUTA
OUTB
x
x
x
x
x
x
x
x
x
< UVLOVDDI,on
> UVLOVDDI,on
> UVLOVDDI,on
x
x
L
L
L
L
L
< UVLOVDDI,on
> UVLOVDDI,on
< UVLOVDDI,on
< UVLOVDDI,on
Follows
INA
x
x
x
> UVLOVDDI,on
< UVLOVDDI,on
> UVLOVDDI,on
L
Follows
INB
2.7
CT communication and input to output data transmission
A coreless transformer (CT) based communication module is used for PWM signal transfer between input and
output. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog
timeout at the receiver side enables recovery from communication fails and ensures safe system shut-down in
failure cases.
Datasheet
9
Rev. 1.4
2023-10-30
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