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2EDN8524FXTMA1 PDF预览

2EDN8524FXTMA1

更新时间: 2024-01-23 04:57:50
品牌 Logo 应用领域
英飞凌 - INFINEON 驱动光电二极管接口集成电路
页数 文件大小 规格书
31页 911K
描述
Buffer/Inverter Based Peripheral Driver, PDSO8, DSO-8

2EDN8524FXTMA1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:SOP,
Reach Compliance Code:compliant风险等级:1.69
内置保护:UNDER VOLTAGE接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码:R-PDSO-G8长度:4.93 mm
湿度敏感等级:1功能数量:1
端子数量:8输出电流流向:SOURCE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1.73 mm
最大供电电压:20 V最小供电电压:4.5 V
标称供电电压:12 V表面贴装:YES
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
断开时间:0.023 µs接通时间:0.023 µs
宽度:3.94 mmBase Number Matches:1

2EDN8524FXTMA1 数据手册

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EiceDRIVER™  
2EDN752x / 2EDN852x  
Product Versions  
1.1  
Logic Versions  
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:  
x=3: inverting input logic  
x=4: non-inverting / direct input logic  
The logic relations between inputs, enable pins and outputs are given in Table 2 for the inverting and non-  
inverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective  
input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage  
lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal.  
Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configurations).  
Table 2  
Logic Table  
Inputs  
Output Inverting  
Output Standard  
ENA  
x
ENB  
x
INA  
INB  
x
UVLO1)  
active  
OUTA  
OUTB  
OUTA  
OUTB  
x
L
L
L
L
L
L
x
x
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
L
L
L
L
H
H
L
L
L
H
x
x
H
L
L
L
L
L
x
L
H
L
L
H
H
H
H
H
H
L
L
H
L
L
L
x
H
L
L
L
H
L
H
H
H
H
L
H
L
H
H
L
H
H
L
L
L
H
L
L
H
H
H
H
H
L
L
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.  
Active means that UVLO disable active the output stages.  
1.2  
Package Versions  
The logic and UVLO versions are available in 3 different packages.  
a standard PG-DSO-8-60 (designated by “F”)  
a small PG-TSSOP-8-1 (designated by “R”)  
a leadless PG-WSON-8-3 (designated by “G”)  
Drawings can be viewed in Chapter 8 (Outline Dimensions).  
Data Sheet  
5
Rev.2.5  
2018-04-20  
 

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