Datasheet > 2ED24427N01F

2ED24427N01F

更新时间： 2023-09-03 20:39:33

品牌	Logo	应用领域
英飞凌 - INFINEON		PC 驱动双极性晶体管
页数	文件大小	规格书
21页	1267K
描述
EiceDRIVER™ 24 V dual-channel low-side non-inverting gate driver for MOSFETs or IGBTs with typical 10 A source and sink currents in a DSO-8 package with thermally efficient, exposed power pad. 2ED24427N01F enables higher power and faster switching frequencies in multiple applications with a reduced PCB footprint and increased reliability by simplifying high power density system design.

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2ED24427N01F 数据手册

2ED24427N01F

10 A dual-channel low-side gate driver IC



V*µs ratings: this factor must be respected, in bipolar drive application (like the one shown in Figure 5) a

maximum of up to twice that parameter is still acceptable for most manufacturers, this factor then must be

chosen accordingly to the following formula:

ꢀ푝ꢁꢂ푚∗훿

(

)

푉 ∗ µ푠 푟푎푡푖푛푔 ∗ 2 ≥

(1)

푓ꢃ푤

where Vprim is the voltage applied to the primary, δ is the duty cycle and fsw the switching frequency of the

application.



N, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio between

primary and secondary.

Lp, primary inductance: this value determines the magnetizing inductance as follows:

퐿ꢄ = 퐿ꢅ ∗ 퐾

(2)

where K is the coupling factor between primary and secondary windings.

L_LK, leakage inductance: this parameter, usually indicated at primary, is equal to:

퐿_ꢆꢇ= 퐿ꢅ ∗ (1 − 퐾)



(3)

The higher Lm is, the lower is the magnetizing current flowing into the transformer and consequent power losses into the

driver. On the other hand the lower L_LKis, the lower and shorter will be the ringing of the secondary LC network created by

L_LK, and Ciss of the fet, damped by Rgss and much lower overshot will appear on the Vgs across the Fet during transition.

Then a too high Lm requires a very good mechanical construction of the gate transformer to achieve high K and

consequent low L_LK.

In a gate driver application running in the range of 50 kHz-200 kHz and using the 2ED24427N01F, a good choice is usually a

Lm between 300 µH and 2 mH and a L_LK< 1µH. This translate for the formula (2) and (3) above in a coupling factor K

between 0.9940 and 0.9995

For good operation and to reduce unneeded power losses into the 2ED24427N01F driver, the magnetizing current has to

be kept I_LM< 0.5 A, from this then derives a minimum Lm to be calculated as follows:

ꢀꢉ

0.5

훿

퐿ꢄ_푚ꢂꢈ

∗

(4)

푓ꢃ푤

Where Vg is the gate driving voltage of the Fet

Figure 6 shows a good design waveform obtained with the following parameters:

Vg =+/-15 V, Lm = 400 µH, L_LK= 0.4 µH, N = 1, fsw = 100 kHz, Ciss_FET= 10 nF, Rg,ps = 3Ω, Rg,ss = 4Ω, and Cdec = 1 µF

Cdec is the AC coupling capacitor needed to reset the driver transformer flux, its value has to be calculated in a way that

the voltage across it can be considered constant during normal operation. The higher the fsw the smaller will be Cdec. A

ceramic capacitor is normally used.

Datasheet

www.infineon.com/gdLowSide

9 of 21

V 2.0

2019-11-10

1...6 7 8910 11 12...21

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