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29109BRA PDF预览

29109BRA

更新时间: 2024-01-08 18:04:40
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路静态存储器
页数 文件大小 规格书
7页 45K
描述
16K x 1 Asynchronous CMOS Static RAM

29109BRA 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:,针数:20
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.72
最长访问时间:70 nsJESD-30 代码:R-GDIP-T20
内存密度:16384 bit内存集成电路类型:STANDARD SRAM
内存宽度:1功能数量:1
端子数量:20字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:16KX1封装主体材料:CERAMIC, GLASS-SEALED
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:SERIAL认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL

29109BRA 数据手册

 浏览型号29109BRA的Datasheet PDF文件第1页浏览型号29109BRA的Datasheet PDF文件第2页浏览型号29109BRA的Datasheet PDF文件第3页浏览型号29109BRA的Datasheet PDF文件第4页浏览型号29109BRA的Datasheet PDF文件第5页浏览型号29109BRA的Datasheet PDF文件第7页 
HM-65262  
Timing Waveforms (Continued)  
(8) TAVAX  
A
(20) TAVEH  
(21) TELEH  
(19) TEHAX  
(18) TAVEL  
E
(22) TWLEH  
W
D
(16) TWHQX  
(24)  
TEHDX  
(23) TDVEH  
(4) TELQX  
Q
(15) TWLQZ  
(7) TEHQZ  
NOTE:  
1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding  
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.  
FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)  
Low Voltage Data Retention  
Intersil CMOS RAMs are designed with battery backup in  
mind. Data retention voltage and supply current are guaran-  
teed over temperature. The following rules ensure data  
retention:  
the deselected state to keep the RAM outputs high  
impedance, minimizing power dissipation.  
3. Inputs which are to be held high (e.g., E) must be kept  
between V  
+0.3V and 70% of V  
during the power  
CC  
up and down transitions.  
CC  
1. Chip Enable (E) must be held high during data retention;  
within V  
to V +0.3V.  
CC  
CC  
4. The RAM can begin operation > 55ns after V  
the minimum operating voltage (4.5V).  
reaches  
CC  
2. On RAMs which have selects or output enables (e.g., S,  
G), one of the selects or output enables should be held in  
DATA RETENTION  
MODE  
V
V
2.0V  
CC  
E
4.5V  
4.5V  
CC  
>55ns  
V
-0.3V TO V  
+0.3V  
CC  
CC  
FIGURE 5. DATA RETENTION TIMING  
6-6  

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