82815 GMCH
R
4.
Functional Description.............................................................................................................. 121
4.1.
System Address Map .................................................................................................. 121
4.1.1.
4.1.2.
4.1.3.
Memory Address Ranges.......................................................................... 122
Compatibility Area ..................................................................................... 123
Extended Memory Area............................................................................. 125
4.1.3.1.
System Management Mode (SMM) Memory Range .................... 128
4.2.
4.3.
Memory Shadowing..................................................................................................... 129
I/O Address Space ...................................................................................................... 129
4.3.1.
4.3.2.
GMCH Decode Rules and Cross-Bridge Address Mapping...................... 129
Address Decode Rules.............................................................................. 130
4.3.2.1.
4.3.2.2.
AGP Interface Decode Rules........................................................ 131
Legacy VGA Ranges .................................................................... 132
4.4.
4.5.
Host Interface .............................................................................................................. 133
4.4.1.
4.4.2.
Host Bus Device Support .......................................................................... 133
Special Cycles........................................................................................... 135
System Memory DRAM Interface................................................................................ 136
4.5.1.
DRAM Organization and Configuration ..................................................... 136
4.5.1.1.
4.5.1.2.
Configuration Mechanism For DIMMs.......................................... 137
DRAM Register Programming...................................................... 138
4.5.2.
4.5.3.
4.5.4.
4.5.5.
DRAM Address Translation and Decoding................................................ 138
DRAM Array Connectivity.......................................................................... 139
SDRAMT Register Programming .............................................................. 140
SDRAM Paging Policy............................................................................... 140
4.6.
4.7.
Intel Dynamic Video Memory Technology (D.V.M.T.)................................................ 140
Display Cache Interface............................................................................................... 141
4.7.1.
4.7.2.
4.7.3.
4.7.4.
Supported DRAM Types for Display Cache Memory................................ 141
Memory Configurations ............................................................................. 142
Address Translation .................................................................................. 143
Display Cache Interface Timing ................................................................ 143
4.8.
Internal Graphics Device ............................................................................................. 144
4.8.1.
4.8.2.
4.8.3.
4.8.4.
4.8.5.
4.8.6.
4.8.7.
3D/2D Instruction Processing.................................................................... 144
3D Engine.................................................................................................. 145
Buffers....................................................................................................... 145
Setup ......................................................................................................... 146
Texturing.................................................................................................... 146
2D Operation ............................................................................................. 148
Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines......................... 148
4.8.7.1.
4.8.7.2.
Fixed BLT Engine ......................................................................... 149
Arithmetic Stretch BLT Engine...................................................... 149
4.8.8.
4.8.9.
4.8.10.
4.8.11.
4.8.12.
4.8.13.
Hardware Motion Compensation............................................................... 149
Hardware Cursor ....................................................................................... 150
Overlay Engine .......................................................................................... 150
Display....................................................................................................... 151
Flat Panel/Digital CRT Interface / 1.8V TV-Out Interface.......................... 152
DDC (Display Data Channel)..................................................................... 153
4.9.
System Reset for the GMCH....................................................................................... 154
4.10. System Clock Description............................................................................................ 154
4.11. Power Management .................................................................................................... 154
4.11.1.
Specifications Supported........................................................................... 154
6
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