82815 GMCH
R
Contents
1.
Overview.....................................................................................................................................13
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
Related Documents .......................................................................................................13
The Intel 815 Chipset Family........................................................................................14
82815 GMCH Overview .................................................................................................16
Host Interface.................................................................................................................17
System Memory Interface ..............................................................................................17
Multiplexed AGP and Display Cache Interface ..............................................................18
1.6.1.
1.6.2.
AGP Interface ..............................................................................................18
Display Cache Interface...............................................................................18
1.7.
1.8.
Hub Interface..................................................................................................................18
82815 GMCH Integrated Graphics Support...................................................................19
1.8.1.
Display, Digital Video Out, and LCD/Flat Panel/Digital CRT........................19
1.9.
System Clocking ............................................................................................................20
1.10. GMCH Power Delivery...................................................................................................20
2.
Signal Description.......................................................................................................................21
2.1.
2.2.
2.3.
Host Interface Signals....................................................................................................22
System Memory Interface Signals .................................................................................23
AGP Interface Signals....................................................................................................24
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
AGP Addressing Signals..............................................................................24
AGP Flow Control Signals............................................................................25
AGP Status Signals .....................................................................................25
AGP Clocking Signals (Strobes)..................................................................26
AGP FRAME# Signals.................................................................................27
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
Display Cache Interface Signals ....................................................................................29
Hub Interface Signals.....................................................................................................30
Display Interface Signals................................................................................................30
Digital Video Output Signals/TV-Out Pins......................................................................31
Power Signals ................................................................................................................32
Clock Signals .................................................................................................................32
2.10. GMCH Power-Up/Reset Strap Options..........................................................................33
2.11. Multiplexed Display Cache and AGP Signal Mapping....................................................34
2.11.1.
Display Cache Mapping at the AGP Connector...........................................35
3.
Configuration Registers ..............................................................................................................37
3.1.
3.2.
Register Nomenclature and Access Attributes ..............................................................37
PCI Configuration Space Access...................................................................................38
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
PCI Bus Configuration Mechanism..............................................................38
Logical PCI Bus #0 Configuration Mechanism.............................................39
Primary PCI (PCI0) and Downstream Configuration Mechanism................39
Internal Graphics Device Configuration Mechanism....................................39
GMCH Register Introduction........................................................................39
3.3.
I/O Mapped Registers ....................................................................................................40
3.3.1.
3.3.2.
CONF_ADDRConfiguration Address Register.........................................40
CONF_DATAConfiguration Data Register...............................................41
Datasheet
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