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28C64AF-15I/TS PDF预览

28C64AF-15I/TS

更新时间: 2024-09-25 21:05:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 67K
描述
8K X 8 EEPROM 5V, 150 ns, PDSO28, 8 X 20 MM, PLASTIC, TSOP-28

28C64AF-15I/TS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:8 X 20 MM, PLASTIC, TSOP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.14Is Samacsys:N
最长访问时间:150 ns其他特性:AUTOMATIC WRITE
命令用户界面:NO数据轮询:YES
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:18.4 mm内存密度:65536 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP28/32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V编程电压:5 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:1.2 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:NO
宽度:8 mm最长写入周期时间 (tWC):1 ms
Base Number Matches:1

28C64AF-15I/TS 数据手册

 浏览型号28C64AF-15I/TS的Datasheet PDF文件第2页浏览型号28C64AF-15I/TS的Datasheet PDF文件第3页浏览型号28C64AF-15I/TS的Datasheet PDF文件第4页浏览型号28C64AF-15I/TS的Datasheet PDF文件第5页浏览型号28C64AF-15I/TS的Datasheet PDF文件第6页浏览型号28C64AF-15I/TS的Datasheet PDF文件第7页 
28C64A  
64K (8K x 8) CMOS EEPROM  
FEATURES  
PACKAGE TYPES  
• Fast Read Access Time—150 ns  
• CMOS Technology for Low Power Dissipation  
- 30 mA Active  
RDY/BSY  
A12  
A7  
• 1  
2
28 Vcc  
27 WE  
26 NC  
25 A8  
3
A6  
4
A6  
A5  
A4  
A3  
A2  
A1 10  
A0 11  
NC 12  
I/O0 13  
5
6
7
8
9
29 A8  
28 A9  
A5  
5
24 A9  
- 100 µA Standby  
A4  
6
23 A11  
22 OE  
21 A10  
20 CE  
19 I/O7  
18 I/O6  
17 I/O5  
16 I/O4  
15 I/O3  
27 A11  
26 NC  
25 OE  
24 A10  
23 CE  
22 I/O7  
21 I/O6  
• Fast Byte Write Time—200 µs or 1 ms  
• Data Retention >200 years  
• High Endurance - Minimum 100,000 Erase/Write  
Cycles  
• Automatic Write Operation  
- Internal Control Timer  
A3  
7
A2  
8
A1  
9
A0  
10  
11  
12  
13  
I/O0  
I/O1  
I/O2  
VSS 14  
- Auto-Clear Before Write Operation  
- On-Chip Address and Data Latches  
• Data Polling  
• Ready/Busy  
• Chip Clear Operation  
• Pin 1 indicator on PLCC on top of package  
OE  
A11  
A9  
1
2
3
4
5
6
7
28  
A10  
27 CE  
26 I/07  
25 I/06  
24 I/05  
23 I/04  
22 I/03  
A8  
NC  
WE  
Vcc  
• Enhanced Data Protection  
- VCC Detector  
- Pulse Filter  
- Write Inhibit  
21  
RDY/BSY  
A12  
8
9
Vss  
20 I/02  
19 I/01  
18 I/00  
17 A0  
16 A1  
15 A2  
A7 10  
A6 11  
A5 12  
A4 13  
A3 14  
• Electronic Signature for Device Identification  
• 5-Volt-Only Operation  
• Organized 8Kx8 JEDEC Standard Pinout  
- 28-pin Dual-In-Line Package  
- 32-pin PLCC Package  
- 28-pin Thin Small Outline Package (TSOP)  
8x20mm  
- 28-pin Very Small Outline Package (VSOP)  
8x13.4mm  
OE  
A11  
A9  
A8  
NC  
WE  
22  
23  
24  
25  
26  
27  
A10  
CE  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
28  
1
VCC  
RDY/BSY  
A12  
A7  
V
SS  
2
3
4
5
6
7
I/O2  
I/O1  
I/O0  
A0  
A1  
A2  
• Available for Extended Temperature Ranges:  
- Commercial: 0˚C to +70˚C  
A6  
A5  
A4  
A3  
8
DESCRIPTION  
BLOCK DIAGRAM  
The Microchip Technology Inc. 28C64A is a CMOS 64K non-  
volatile electrically Erasable PROM. The 28C64A is  
accessed like a static RAM for the read or write cycles without  
the need of external components. During a “byte write”, the  
address and data are latched internally, freeing the micropro-  
cessor address and data bus for other operations. Following  
the initiation of write cycle, the device will go to a busy state  
and automatically clear and write the latched data using an  
internal control timer. To determine when the write cycle is  
complete, the user has a choice of monitoring the Ready/  
Busy output or using Data polling. The Ready/Busy pin is an  
open drain output, which allows easy configuration in wired-  
or systems. Alternatively, Data polling allows the user to read  
the location last written to when the write operation is com-  
plete. CMOS design and processing enables this part to be  
used in systems where reduced power consumption and reli-  
ability are required. A complete family of packages is offered  
to provide the utmost flexibility in applications  
I/O0  
I/O7  
VSS  
Data Protection  
VCC  
Circuitry  
Chip Enable/  
Output Enable  
Control Logic  
CE  
OE  
WE  
Input/Output  
Buffers  
Auto Erase/Write  
Timing  
Data  
Poll  
Rdy/  
Busy  
Program Voltage  
Generation  
A0  
Y
Y Gating  
Decoder  
L
a
t
c
h
e
s
16K bit  
Cell Matrix  
X
Decoder  
A12  
1996 Microchip Technology Inc.  
DS11109H-page 1  
This document was created with FrameMaker 4 0 4  

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