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27LV256-30I/VS PDF预览

27LV256-30I/VS

更新时间: 2024-02-26 20:33:12
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27LV256-30I/VS 数据手册

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27LV256  
256K (32K x 8) Low-Voltage CMOS EPROM  
FEATURES  
PACKAGE TYPES  
PDIP  
• Wide voltage range 3.0V to 5.5V  
• High speed performance  
VPP • 1  
28 VCC  
27 A14  
26 A13  
25 A8  
24 A9  
23 A11  
22 OE  
21 A10  
20 CE  
19 O7  
18 O6  
17 O5  
16 O4  
15 O3  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
O0  
O1  
O2  
2
3
4
- 200 ns access time available at 3.0V  
• CMOS Technology for low power consumption  
- 8 mA Active current at 3.0V  
5
6
7
8
- 20 mA Active current at 5.5V  
9
10  
11  
12  
13  
- 100 µA Standby current  
• Factory programming available  
• Auto-insertion-compatible plastic packages  
• Auto ID aids automated programming  
• Separate chip enable and output enable controls  
• High speed “Express” programming algorithm  
• Organized 32K x 8: JEDEC standard pinouts  
- 28-pin Dual-in-line package  
VSS 14  
PLCC  
5
29  
A6  
A8  
6
28  
A5  
A4  
A3  
A2  
A1  
A0  
NC  
O0  
A9  
7
27  
A11  
- 32-pin PLCC package  
8
26  
25  
24  
23  
22  
21  
NC  
OE  
A10  
CE  
O7  
O6  
9
- 28-pin SOIC package  
10  
11  
12  
13  
- 28-pin VSOP package  
- Tape and reel  
• Data Retention > 200 years  
• Available for the following temperature ranges:  
- Commercial:  
- Industrial:  
0˚C to +70˚C  
SOIC  
-40˚C to +85˚C  
VPP  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
A14  
A13  
A8  
2
3
DESCRIPTION  
A6  
4
A5  
5
A9  
The Microchip Technology Inc. 27LV256 is a low volt-  
age (3.0 volt) CMOS EPROM designed for battery  
powered applications. The device is organized as a  
32K x 8 (32K-Byte) non-volatile memory product. The  
27LV256 consumes only 8 mA maximum of active cur-  
rent during a 3.0 volt read operation therefore improv-  
ing battery performance. This device is designed for  
very low voltage applications where conventional 5.0  
volt only EPROMS can not be used. Accessing individ-  
ual bytes from an address transition or from power-up  
(chip enable pin going low) is accomplished in less than  
200 ns at 3.0V. This device allows systems designers  
the ability to use low voltage non-volatile memory with  
today’s' low voltage microprocessors and peripherals  
in battery powered applications.  
A4  
6
A11  
OE  
A10  
CE  
O7  
A3  
7
A2  
8
A1  
9
A0  
10  
11  
12  
13  
14  
O0  
O1  
O2  
VSS  
O6  
O5  
O4  
O3  
VSOP  
OE  
A11  
A9  
A8  
A13  
A14  
22  
23  
24  
25  
26  
27  
A10  
CE  
O7  
O6  
O5  
O4  
O3  
VSS  
O2  
O1  
O0  
A0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
28  
1
VCC  
VPP  
A complete family of packages is offered to provide the  
most flexibility in applications. For surface mount appli-  
cations, PLCC, VSOP or SOIC packaging is available.  
Tape and reel packaging is also available for PLCC or  
SOIC packages.  
2
3
4
5
6
7
A12  
A7  
A6  
A5  
A4  
A3  
A1  
A2  
8
1996 Microchip Technology Inc.  
DS11020F-page 1  
This document was created with FrameMaker 4 0 4  

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