27C256
FIGURE 1-2: PROGRAMMING WAVEFORMS
Program
Verify
V
V
V
V
IH
IL
Address
Data
Address Stable
t
AS
t
AH
IH
IL
High Z
Data Stable
Data Out Valid
t
DF
t
DS
tDH
(1)
13.0V(2)
5.0V
V
PP
t
t
VPS
VCS
6.5V(2)
5.0V
V
CC
V
V
V
V
IH
IL
CE
OE
t
OES
t
PW
t
OE
IH
IL
(1)
Notes:
(1)
(2)
tDF and tOE are characteristics of the device but must be accommodated by the programmer
V
CC = 6.5 V ±0.25V, V PP = V
H
= 13.0V ±0.25V for express algorithm
TABLE 1-6:
MODES
Operation Mode
Read
CE
OE
VPP
A9
O0 - O7
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIL
VIH
X
VCC
VH
X
X
DOUT
DIN
Program
Program Verify
Program Inhibit
Standby
VH
X
DOUT
VH
X
High Z
VCC
VCC
VCC
X
High Z
Output Disable
Identity
VIH
VIL
X
High Z
VH
Identity Code
X = Don’t Care
1.2
Read Mode
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a) the CE pin is low to power up (enable) the chip
b) the OE pin is low to gate the data to the output
pins
2004 Microchip Technology Inc.
DS11001N-page 5