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27C128-17I/L PDF预览

27C128-17I/L

更新时间: 2024-01-31 19:41:13
品牌 Logo 应用领域
美国微芯 - MICROCHIP 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 65K
描述
x8 EPROM

27C128-17I/L 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:8 X 13.40 MM, TSOP-28针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.67
Is Samacsys:N最长访问时间:170 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0内存密度:131072 bit
内存集成电路类型:OTP ROM内存宽度:8
功能数量:1端子数量:28
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP28/32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V编程电压:13 V
认证状态:Not Qualified最大待机电流:0.0001 A
子类别:OTP ROMs最大压摆率:0.025 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

27C128-17I/L 数据手册

 浏览型号27C128-17I/L的Datasheet PDF文件第3页浏览型号27C128-17I/L的Datasheet PDF文件第4页浏览型号27C128-17I/L的Datasheet PDF文件第5页浏览型号27C128-17I/L的Datasheet PDF文件第7页浏览型号27C128-17I/L的Datasheet PDF文件第8页浏览型号27C128-17I/L的Datasheet PDF文件第9页 
27C128  
1.3  
Standby Mode  
1.7  
Verify  
The standby mode is defined when the CE pin is high  
(VIH) and a program mode is not defined.  
After the array has been programmed it must be veri-  
fied to ensure all the bits have been correctly pro-  
grammed. This mode is entered when all the following  
conditions are met:  
When these conditions are met, the supply current will  
drop from 20 mA to 100 µA.  
a) VCC is at the proper level,  
b) VPP is at the proper VH level,  
c) the CE line is low,  
1.4  
Output Enable  
This feature eliminates bus contention in microproces-  
sor-based systems in which multiple devices may drive  
the bus. The outputs go into a high impedance state  
when the following condition is true:  
d) the PGM line is high, and  
e) the OE line is low.  
1.8  
Inhibit  
• The OE and PGM pins are both high.  
When programming multiple devices in parallel with dif-  
ferent data, only CE or PGM need be under separate  
control to each device. By pulsing the CE or PGM line  
low on a particular device in conjunction with the PGM  
or CE line low, that device will be programmed; all other  
devices with CE or PGM held high will not be pro-  
grammed with the data, although address and data will  
be available on their input pins (i.e., when a high level  
is present on CE or PGM); and the device is inhibited  
from programming.  
1.5  
Erase Mode (U.V. Windowed Versions)  
Windowed products offer the capability to erase the  
memory array. The memory matrix is erased to the all  
1’s state when exposed to ultraviolet light. To ensure  
2
complete erasure, a dose of 15 watt-second/cm is  
required. This means that the device window must be  
placed within one inch and directly underneath an ultra-  
violet lamp with a wavelength of 2537 Angstroms,  
2
intensity of 12,000µW/cm for approximately 20 min-  
utes.  
1.9  
Identity Mode  
1.6  
Programming Mode  
In this mode specific data is output which identifies the  
manufacturer as Microchip Technology Inc. and device  
type. This mode is entered when Pin A9 is taken to VH  
(11.5V to 12.5V). The CE and OE lines must be at VIL.  
A0 is used to access any of the two non-erasable bytes  
whose data appears on O0 through O7.  
The Express Algorithm has been developed to improve  
the programming throughput times in a production  
environment. Up to ten 100-microsecond pulses are  
applied until the byte is verified. No overprogramming  
is required. A flowchart of the express algorithm is  
shown in Figure 1-3.  
Programming takes place when:  
Pin  
Identity  
Input  
A0  
Output  
a) VCC is brought to the proper voltage,  
b) VPP is brought to the proper VH level,  
c) the CE pin is low,  
H
e
x
0 O O O O O O O  
7
6
5
4
3
2
1
0
d) the OE pin is high, and  
Manufacturer  
Device Type*  
VIL  
VIH  
0
1
0
0
1
0
0
0
1
0
0
0
0
1
1
1
29  
83  
e) the PGM pin is low.  
Since the erased state is “1” in the array, programming  
of “0” is required. The address to be programmed is set  
via pins A0-A13 and the data to be programmed is pre-  
sented to pins O0-O7. When data and address are sta-  
ble, OE is high, CE is low and a low-going pulse on the  
PGM line programs that location.  
* Code subject to change  
DS11003K-page 6  
1996 Microchip Technology Inc.  

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