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25AA1024T-I/SM PDF预览

25AA1024T-I/SM

更新时间: 2024-02-09 21:52:00
品牌 Logo 应用领域
美国微芯 - MICROCHIP 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
30页 573K
描述
1 Mbit SPI Bus Serial EEPROM

25AA1024T-I/SM 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.3针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.5
Is Samacsys:N最大时钟频率 (fCLK):20 MHz
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:5.28 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:2/5 V
编程电压:1.8 V认证状态:Not Qualified
座面最大高度:2.03 mm串行总线类型:SPI
最大待机电流:0.000001 A子类别:Flash Memories
最大压摆率:0.01 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
类型:NOR TYPE宽度:5.21 mm
最长写入周期时间 (tWC):5 ms写保护:HARDWARE/SOFTWARE
Base Number Matches:1

25AA1024T-I/SM 数据手册

 浏览型号25AA1024T-I/SM的Datasheet PDF文件第3页浏览型号25AA1024T-I/SM的Datasheet PDF文件第4页浏览型号25AA1024T-I/SM的Datasheet PDF文件第5页浏览型号25AA1024T-I/SM的Datasheet PDF文件第7页浏览型号25AA1024T-I/SM的Datasheet PDF文件第8页浏览型号25AA1024T-I/SM的Datasheet PDF文件第9页 
25AA1024/25LC1024  
2.0  
2.1  
FUNCTIONAL DESCRIPTION  
Principles of Operation  
BLOCK DIAGRAM  
STATUS  
Register  
HV Generator  
The 25XX1024 is a 131,072 byte Serial EEPROM  
designed to interface directly with the Serial Peripheral  
Interface (SPI) port of many of today’s popular  
microcontroller families, including Microchip’s PIC®  
microcontrollers. It may also interface with microcon-  
trollers that do not have a built-in SPI port by using  
discrete I/O lines programmed properly in firmware to  
match the SPI protocol.  
EEPROM  
Array  
Memory  
Control  
Logic  
X
I/O Control  
Logic  
Dec  
Page Latches  
Y Decoder  
The 25XX1024 contains an 8-bit instruction register.  
The device is accessed via the SI pin, with data being  
clocked in on the rising edge of SCK. The CS pin must  
be low and the HOLD pin must be high for the entire  
operation.  
SI  
SO  
CS  
SCK  
Table 2-1 contains a list of the possible instruction  
bytes and format for device operation. All instructions,  
addresses and data are transferred MSB first, LSB last.  
Sense Amp.  
R/W Control  
HOLD  
WP  
VCC  
VSS  
Data (SI) is sampled on the first rising edge of SCK  
after CS goes low. If the clock line is shared with other  
peripheral devices on the SPI bus, the user can assert  
the HOLD input and place the 25XX1024 in ‘HOLD’  
mode. After releasing the HOLD pin, operation will  
resume from the point when the HOLD was asserted.  
TABLE 2-1:  
INSTRUCTION SET  
Instruction Name  
Instruction Format  
Description  
READ  
WRITE  
WREN  
WRDI  
RDSR  
WRSR  
PE  
0000 0011  
0000 0010  
0000 0110  
0000 0100  
0000 0101  
0000 0001  
0100 0010  
1101 1000  
1100 0111  
1010 1011  
1011 1001  
Read data from memory array beginning at selected address  
Write data to memory array beginning at selected address  
Set the write enable latch (enable write operations)  
Reset the write enable latch (disable write operations)  
Read STATUS register  
Write STATUS register  
Page Erase – erase one page in memory array  
Sector Erase – erase one sector in memory array  
Chip Erase – erase all sectors in memory array  
Release from Deep power-down and read electronic signature  
Deep Power-Down mode  
SE  
CE  
RDID  
DPD  
DS21836D-page 6  
Preliminary  
© 2007 Microchip Technology Inc.  

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