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2510-6002UB

更新时间： 2024-02-06 01:32:13
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德州仪器 - TI 转换器连接器PC
页数 文件大小 规格书
9页 245K
描述
High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS

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2510-6002UB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.33
其他特性：3M, LOW PROFILE主体宽度：0.338 inch
主体深度：0.38 inch主体长度：0.788 inch
连接器类型：BOARD CONNECTOR联系完成配合：GOLD (15) OVER NICKEL (100)
联系完成终止：Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier触点性别：MALE
触点材料：COPPER ALLOY触点模式：RECTANGULAR
触点样式：SQ PIN-SKTDIN 符合性：NO
介电耐压：1400VAC V滤波功能：NO
IEC 符合性：NO绝缘电阻：1000000000 Ω
绝缘体颜色：GRAY绝缘体材料：GLASS FILLED POLYBUTYLENE TEREPHTHALATE
JESD-609代码：e0MIL 符合性：NO
插接触点节距：0.1 inch匹配触点行间距：0.1 inch
混合触点：NO安装选项1：GUIDE SLOT
安装选项2：LOCKING安装方式：STRAIGHT
安装类型：BOARD连接器数：ONE
PCB行数：2装载的行数：2
最高工作温度：105 °C最低工作温度：-55 °C
选件：GENERAL PURPOSEPCB接触模式：RECTANGULAR
PCB触点行间距：2.54 mm电镀厚度：15u inch
极化密钥：POLARIZED HOUSING额定电流（信号）：2 A
参考标准：UL可靠性：COMMERCIAL
子类别：Headers and Edge Type Connectors端子长度：0.112 inch
端子节距：2.54 mm端接类型：SOLDER
触点总数：10UL 易燃性代码：94V-0
Base Number Matches：1

2510-6002UB 数据手册

 浏览型号2510-6002UB的Datasheet PDF文件第1页浏览型号2510-6002UB的Datasheet PDF文件第3页浏览型号2510-6002UB的Datasheet PDF文件第4页浏览型号2510-6002UB的Datasheet PDF文件第5页浏览型号2510-6002UB的Datasheet PDF文件第6页浏览型号2510-6002UB的Datasheet PDF文件第7页 
Introduction  
www.ti.com  
1
Introduction  
In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential  
problems and ensure reliable performance. Power supply designers must consider the timing and voltage  
differences between core and input/output (I/O) voltage supplies during power-up and power-down  
operations.  
Sequencing refers to the order, timing, and differential in which the two voltage rails are powered up and  
down. A system designed without proper sequencing may be at risk for two types of failures. The first of  
these represents a threat to the long-term reliability of the dual voltage device, whereas the second is  
more immediate, with the possibility of damaging interface circuits in the processor or system devices  
such as memory, logic, or data converter integrated circuits (IC).  
Another potential problem with improper supply sequencing is bus contention. Bus contention is a  
condition in which the processor and another device both attempt to control a bidirectional bus during  
power up. Bus contention may also affect I/O reliability. Power supply designers must check the  
requirements regarding bus contention for individual devices.  
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are  
shown in Table 1. None of the supplies for these devices require a specific voltage ramp rate as long as  
the 3.3-V rail does not exceeds the 1.8-V rail by more than 2 V.  
In order to reduce the power consumption of the processor core, dynamic voltage and frequency scaling  
(DVFS) is used in the reference design. DVFS is a power management technique used while active  
processing is going on in the system-on-chip (SoC), which matches the operating frequency of the  
hardware to the performance requirement of the active application scenario. Whenever clock frequencies  
are lowered, operating voltages are also lowered to achieve power savings. In the reference design, the  
TPS62353 is used, which can scale its output voltage.  
2
Power Requirements  
The power requirements are as specified in the following table.  
Table 1. General Requirements  
(1) (2)  
VOLTAGE  
(V)  
Imax  
(mA)  
SEQUENCING  
ORDER  
TIMING  
DELAY  
PIN NAME  
RTC_CVDD  
CVDD(4)  
TOLERANCE  
I/O  
1.2  
1.0 / 1.1 / 1.2  
1.2  
1
–25%, +10%  
–9.75%, +10%  
–5%, +10%  
1(3)  
Core  
I/O  
600  
200  
2
RVDD, PLL0_VDDA,  
3
PLL1_VDDA, SATA_VDD,  
USB_CVDD, USB0_VDDA12  
I/O  
USB0_VDDA18, USB1_VDDA18,  
DDR_DVDD18, SATA_VDDR,  
DVDD18  
1.8  
180  
±5%  
4
I/O  
I/O  
USB0_VDDA33, USB1_VDDA33  
3.3  
24  
50 / 90(5)  
±5%  
±5%  
5
DVDD3318_A, DVDD3318_B,  
DVDD3318_C  
1.8 / 3.3  
4 / 5  
(1)  
(2)  
If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails  
(VDDA33_USB0/1).  
No specific voltage ramp rate is required for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) as long as  
STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) never exceeds more than 2 V.  
If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.  
If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.  
If DVDD3318_A, B, and C are powered independently, maximum power for each rail is 1/3 above maximum power.  
(3)  
(4)  
(5)  
NanoFree is a trademark of Texas Instruments.  
2
High-Vin, High-Efficiency Power Solution Using DC/DC Converters With DVFS  
SLVA339A–June 2009–Revised May 2010  
Copyright © 2009–2010, Texas Instruments Incorporated  
 
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