24AA512/24LC512/24FC512
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
VCC = +1.7V to 5.5V
VCC = +2.5V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
Sym.
No.
Characteristic
Clock frequency
Min.
Max.
Units
Conditions
FCLK
—
—
—
—
100
400
400
kHz
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
1
2
3
4
1000
THIGH
TLOW
Clock high time
Clock low time
4000
600
600
500
—
—
—
—
ns
ns
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
4700
1300
1300
500
—
—
—
—
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
TR
TF
SDA and SCL rise time (Note 1)
SDA and SCL fall time (Note 1)
—
—
—
1000
300
300
1.7V VCC< 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
—
—
300
100
ns
ns
All except, 24FC512
1.7V VCC 5.5V 24FC512
5
6
THD:STA Start condition hold time
4000
600
600
250
—
—
—
—
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
TSU:STA Start condition setup time
4700
600
600
250
—
—
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
7
THD:DAT Data input hold time
TSU:DAT Data input setup time
0
—
ns
ns
(Note 2)
8
9
250
100
100
—
—
—
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
TSU:STO Stop condition setup time
4000
600
600
250
—
—
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
10
TSU:WP WP setup time
THD:WP WP hold time
4000
600
600
—
—
—
ns
ns
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
11
12
13
4700
1300
1300
—
—
—
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
TAA
Output valid from clock (Note 2)
—
—
—
—
3500
900
900
400
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
TBUF
Bus free time: Time the bus
must be free before a new trans-
mission can start
4700
1300
1300
500
—
—
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
14
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2010 Microchip Technology Inc.
DS21754M-page 3